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Memory macro and method of operating the same

A memory macro and memory cell technology, applied in the semiconductor field, can solve problems such as affecting IC performance and operating voltage reduction

Active Publication Date: 2017-11-28
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As ICs become smaller and more complex, the operating voltages of these digital devices continue to decrease, affecting IC performance

Method used

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  • Memory macro and method of operating the same
  • Memory macro and method of operating the same
  • Memory macro and method of operating the same

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Embodiment Construction

[0024] The following disclosure provides different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, etc. are described below to simplify the present disclosure. Of course, such examples are merely examples and are not limiting. Other components, materials, values, steps, arrangements, etc. are contemplated. For example, in the following detailed description, a first feature formed over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed An embodiment in which the first and second features do not come into direct contact between the first feature and the second feature. Additionally, the present disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not...

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Abstract

A memory macro includes a first memory cell array, a first tracking circuit and a first pre-charge circuit. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line coupled to the first set of memory cells and the second set of memory cells. The first set of pull-down cells and the first set of loading cells are configured to track a memory cell of the first memory cell array. The first pre-charge circuit is coupled to the first tracking bit line, and is configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third set of control signals.

Description

technical field [0001] Embodiments of the present invention relate to the semiconductor field, and more specifically, to a memory macro and an operation method thereof. Background technique [0002] The semiconductor integrated circuit (IC) industry has produced a variety of digital devices to solve problems in many different fields. Some of these digital devices, such as memory macros, are configured for data storage. As ICs become smaller and more complex, the operating voltages of these digital devices continue to decrease, affecting IC performance. Contents of the invention [0003] According to an embodiment of the present invention, a memory macro includes: a first memory cell array, a first tracking circuit, and a first pre-charging circuit. Wherein, the first tracking circuit includes a first group of memory cells, a second group of memory cells and a first tracking bit line. The first group of memory cells is configured as a first group of load cells in respons...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/12G11C7/18
CPCG11C7/12G11C7/18G11C7/227G11C11/419G11C5/14G11C7/06G11C7/10
Inventor 苏建国李政宏郑基廷廖宏仁张琮永陈炎辉潘卡伊·阿加沃尔廖忠志
Owner TAIWAN SEMICON MFG CO LTD