A reliability testing method and system for dual-port memory

Abstract

The invention discloses a reliability testing method and system for a dual-port memory. The method of the present invention includes: a single address read-write correctness test, wherein, write from one interface of the dual-port memory and read from the other interface, check whether the read-write is correct; parameter configuration suitability test; read-write mutual impact testing; and / or address line testing. By adopting the testing method and system of the present invention, problems can be found in the early stage of design, which helps to save design cost. At the same time, the flow of the test method of the present invention is relatively standard, which is beneficial to large-scale applications, and is especially suitable for communication tests between products of different manufacturers, products designed by different designers, and different modules.

Description

Technical field[0001]The present invention relates to the field of computer hardware, and in particular to a reliability test method and system for double-port memory.Background technique[0002]The function of double-port memory (RAM) is to store data and data exchange. In order to achieve access to the same address, there is a corresponding 2 set bus mechanism in physically. From the security of data exchange, the two chips are not allowed to access the same address at the same time, otherwise the data access conflict can be caused. Because of the above reasons, the double-port RAM must use a specific method to coordinate the read and write operations of the two chips to prevent reading errors in data.[0003]Double RAM access has always been one of the difficulties of data interaction between chips. Double-port RAM is extremely difficult to read and write in the work as a communication interface between the chip, and the data area of ​​the sporadic data area is difficult to find, and...

AI Technical Summary

Problems solved by technology

As the dual-port RAM is used as a communication interface between chips, the reading and writing speed is extremely fast during work, and sporadic data area anomalies are difficult to find. In this case, the problem is often hidden

If the device stops running due to this reason, the data in the RAM area will be lost due to power failure, and the abnormal process will be difficult to reproduce.

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