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Resetting system of mounting external memory on basis of FPGA

An external storage and external reset technology, applied in the field of FPGA storage, can solve problems such as the system cannot work normally, the file system is damaged, and cannot communicate with external storage normally, and achieves a reliable design principle, enhanced stability, and outstanding substantive characteristics. Effect

Active Publication Date: 2018-03-06
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If a hard reset is triggered inside the FPGA, since the FPGA hard reset pin can only be used for input and cannot be used for output, that is, when the FPGA is hard reset, the external storage does not perform a reset action,

Method used

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  • Resetting system of mounting external memory on basis of FPGA
  • Resetting system of mounting external memory on basis of FPGA

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Embodiment Construction

[0030] In order to make the purpose, features and advantages of the present invention more obvious and understandable, the technical solutions in the present invention will be clearly and completely described below in conjunction with the drawings in the specific embodiments of the present invention.

[0031] Such as figure 2 As shown, the present invention provides a reset system based on FPGA mounting external storage, including FPGA 1, external storage 2, AND gate 4 and external reset control module 3; FPGA adopts the FPGA of the Cyclone V model of Altera;

[0032] FPGA1 includes FPGA data interface 1.1, soft reset interface 1.2, hard reset interface 1.3 and GPIO 1.4; FPGA data interface 1.1 adopts QSPI interface;

[0033] External storage 2 includes external storage data interface 2.1 and reset interface 2.2; external storage data interface 2.1 adopts QSPI interface; external storage 2 adopts Flash with QSPI interface;

[0034] The external reset control module 3 include...

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PUM

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Abstract

The invention discloses a resetting system of mounting an external memory on the basis of an FPGA. The system includes the FPGA, the external memory, an AND gate and an external resetting control module. A data interface of the FPGA is connected with a data interface of the external memory. An external soft-resetting control unit is connected with a soft-resetting interface of the FPGA and a firstinput end of the AND gate. An external hard-resetting control unit is connected with a hard-resetting interface of the FPGA and a second input end of the AND gate. A resetting interface of the external memory is connected with an output end of the AND gate and GPIO of the FPGA. The AND gate is used for isolating resetting signals from the external memory, and is also used for ensuring that all the resetting signals of soft resetting and hard resetting can carry out resetting operation on the external memory. The GPIO is used for providing a resetting signal to the external memory when hard resetting is triggered inside the FPGA or hard resetting of the FPGA is triggered by software. According to the system, an effect that status of normal communication with the external memory can be maintained after any FPGA resetting operation is realized, and stability of the system is enhanced.

Description

technical field [0001] The invention belongs to the field of FPGA storage, and in particular relates to a reset system for mounting external storage based on FPGA. Background technique [0002] With the enhancement of FPGA performance and the increase in the number of resources, FPGA needs more and more storage space to store data information. Due to the limitation of FPGA volume and the limitation of on-chip ROM capacity, FPGA is forced to expand storage by externally mounting ROM. space. In order to enhance the stability of the system, when a problem occurs in the system, the system will restart by reset. Since the addressing modes of the FPGA and the external storage are different, it is necessary to reset the external storage while resetting the FPGA to ensure that the FPGA and the external storage Normal communication is possible after reset. [0003] Such as figure 1 As shown, the current existing solution is to connect the FPGA soft reset output pin to the reset in...

Claims

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Application Information

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IPC IPC(8): G06F15/78G06F15/76
Inventor 黄冰冰张燕群
Owner ZHENGZHOU YUNHAI INFORMATION TECH CO LTD