Voltage regulator having auto mode optimization for load profiles

[0019] In the following description, for the purpose of explanation, many examples and specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure as expressed in the claims may include some or all of the features in these examples, alone or in combination with other features described below, and may also include the features described herein And the modification and equivalent of the concept.

[0020] figure 1 Shown are configured to produce a regulated output voltage V at output 110 in accordance with the present disclosure out A high-level block diagram of the voltage regulator 100 to drive the load 12. The voltage regulator 100 may include a feedback/control stage 102 and an output stage 104. Can provide feedback signal V from output 110 feedback And through the error amplifier 106 and the reference voltage V ref The comparison is performed to generate an error signal 112. The feedback/control stage 102 may be configured to receive the error signal 112 to generate the control signal 114. The output stage 104 may be configured to receive the control signal 114 and generate an output voltage V based on the control signal 114 out , Thus according to the reference voltage V ref Adjust the output 110.

[0021] According to the present disclosure, the voltage regulator 100 may further include a current sensing circuit 122 configured to generate a current sensing signal 162 indicating the load current I flowing into the load 12 during operation. load. The current sensing signal 162 may be provided to the feedback/control stage 102. As will be discussed in more detail in various embodiments according to the present disclosure below, the load current I load The load condition at output 110 (eg, low load, high load) can be indicated. The feedback/control stage 102 can be based on Figure 3-5 The state transition diagram shown in FIG. 1 controls the output stage 104 according to the load condition at the output 110.

[0022] The discussion will turn to a specific example of the voltage regulator 100 to explain further details of the present disclosure. figure 2 A voltage regulator called a switching voltage regulator, and specifically a step-down regulator 200 is shown. Although the buck regulator 200 will be used as an example, those of ordinary skill will understand that the present disclosure can be adapted to other types of voltage regulators. figure 2 A high-level representation of the buck regulator 200 is depicted, and the actual implementation details are omitted to simplify the discussion.

[0023] The buck regulator 200 can produce a regulated voltage V at the output 210 out To drive the load 22. In some embodiments, the buck regulator 200 may include a feedback/control stage 202 and an output stage 204. Feedback signal V feedback Can be provided from the output 210, and through the error amplifier 232 and the reference voltage V ref The comparison is performed to generate an error signal 212. In some embodiments, the output 210 can be split to generate V feedback , For example, a resistor divider (not shown) is used.

[0024] The feedback/control stage 202 may include a ramp generator 222 configured to generate a ramp signal. The comparator 224 may compare the ramp signal with the error signal 212 to generate a control signal 214. The feedback/control stage 202 may include a switch controller 226 configured to receive the control signal 214 from the comparator 224 to generate the switch signal 216. According to some embodiments of the present disclosure, the feedback/control state 202 may include a hysteresis comparator 228 with hysteresis. This aspect of the present disclosure will be discussed in more detail below.

[0025] The output stage 204 may include a circuit device 242, power switches M1, M2, an inductor L and an output capacitor C. The circuit 242 may include a driver circuit configured to receive the switch signal 216 to generate a gate drive signal 218 that can drive the power switches M1, M2.

[0026] According to the present disclosure, the circuit device 242 may further include a current sensing circuit device configured to generate a current sensing signal 244, the current sensing signal 244 indicating the load current I provided to the load 22 at the output 210 load. In some embodiments, the current sensing signal 244 may represent I load Digital signal. In other embodiments, the current sensing signal 244 may represent I load Analog signal. Load current I load The load condition at the output 210 (eg, low load, high load) can be indicated. The feedback/control stage 202 can be Figure 3-5 The state transition diagram shown in FIG. 2 controls the output stage 204 according to the load condition at the output 210.

[0027] The buck regulator 200 may receive data from the memory 252. The user can provide the data 24 to be stored in the memory 252. The memory 252 may be any suitable non-volatile data storage device, such as flash memory. The data stored in the memory 252 can be used in the switch controller 226 and the hysteresis comparator 228. This aspect of the present disclosure will be discussed below.

[0028] A switching voltage regulator such as the buck regulator 200 may operate in different modes according to the load condition sensed at the output 210. For example, in some embodiments, it may be based on the load current I flowing into the load 22 during the operation of the buck regulator 200. load Determine the load status. The buck regulator 200 may include a first operation mode called a low power mode (LPM mode). When the first load condition is sensed at the output 210, the buck regulator 200 may operate in the LPM mode. In some embodiments, for example, the buck regulator 200 may operate in LPM mode during low load conditions, when the load current I load Less than the first threshold Th low (For example, less than a few hundred milliamps) indicates a low load condition. Depending on the circuit design, the performance rating of the components including the buck regulator 200, and other considerations not related to the present disclosure, Th low The specific value of can vary.

[0029] The buck regulator 200 may include a second operation mode called a normal power mode (NPM mode). When the second load condition is sensed at the output 210, the buck regulator 200 may operate in the NPM mode. For example, in some embodiments, the buck regulator 200 may operate in NPM mode during high load conditions when the load current I load Above the second threshold Th high (For example, more than a few hundred milliamps) can indicate high load conditions. Depending on the circuit design, the performance rating of the components including the buck regulator 200, and other considerations not related to the present disclosure, Th high The specific value of can vary.

[0030] During the NPM mode, the power switches M1, M2 are always switched to maintain the current flow across the inductor L so as to maintain the voltage at the output 210 above the reference voltage. NPM mode is sometimes called continuous current mode.

[0031] However, under sufficiently low load conditions, the output capacitor C can maintain the output voltage for a period of time between switching pulses. Therefore, it is possible to allow the output voltage at the output 210 to drop below the reference voltage, while still being able to supply power to the load 22. Therefore, under a low load condition, the buck regulator 200 can operate in the LPM mode, where the switches of M1 and M2 can skip one or more clock cycles to reduce the inductor current to zero. LPM mode is sometimes called power saving mode, pulse omission mode, and so on.

[0032] Changing the operation of the buck regulator 200 between the LPM mode and the NPM mode may automatically occur as the load condition changes between a low load condition and a high load condition. However, if the load condition changes too quickly, the buck regulator 200 may continuously change between the LPM and NPM modes in a cyclic manner. Therefore, the buck regulator 200 may spend most of its time in the mode switching state instead of the static mode. According to the present disclosure, the buck regulator 200 can be maintained in the NPM mode during the dynamic load burst "envelope", and the load condition changes faster than the programmable time period during the dynamic load burst "envelope". Now discuss this aspect of the disclosure.

[0033] image 3 A state transition diagram 300 according to the present disclosure is shown. The state transition diagram 300 represents operations in the switch controller 226 for switching the operation of the buck regulator 200 between a first operation mode (e.g., LPM mode) and a second operation mode (e.g., NPM mode). Without loss of generality, the description of the state transition diagram 300 may begin with the switch controller 226 in the state 302 (LPM mode). In response to the occurrence of a low load to high load event 312, the switch controller 226 may switch the operation of the buck regulator 200 from the LPM mode to the NPM mode. In some embodiments, for example, when the load current I sensed at the output 210 is load From less than the low current threshold level (for example, Th low ) Becomes greater than the high current threshold level (for example, Th high ), the low load to high load event 312 can be signaled.

[0034] The switch controller 226 can transition from the state 302 to the transition state 304. The conversion may include the switch controller 226 asserting the exit_LPM signal to set the operation of the buck regulator 200 in the NPM mode. The switch controller 226 can start or otherwise start the timer T1. In some embodiments, a transition state 304 may be included to provide a stable period to allow the circuit including the buck regulator 200 to stabilize when the circuit changes from operating in the LPM mode to operating in the NPM mode. In other embodiments, the transition state 304 may be omitted. In response to the expiration of the timer T1 (event 314) or completion in other ways, the switch controller 226 may transition from the transition state 304 to the state 306 (NPM mode), thereby completing the transition from operating the buck regulator 200 in LPM mode to operating in NPM Mode operation conversion.

[0035] The operation of the buck regulator 200 may remain in the NPM mode until a high load to low load event occurs. However, as explained above, according to the present disclosure, if the load condition is too dynamic, the buck regulator 200 may remain in the NPM mode until the load condition becomes less dynamic.

[0036] Continue to refer image 3 The state transition diagram 300 provides an example of handling over-dynamic load conditions according to some embodiments of the present disclosure. When the buck regulator 200 transitions from the state 304 to the state 306, the transition may include starting a timer T2. As long as the timer T2 is running, the switch controller 226 can remain in the NPM mode (state 306), regardless of any changes in load conditions.

[0037] According to some embodiments, if a low-load to high-load transition is sensed while the timer T2 is still running (event 316), the timer T2 may be restarted to switch the controller 226 on and off in another cycle of the timer T2 Maintain the NPM mode (state 306). Since the timer T2 is reset whenever the event 316 occurs, it is only made if the change in the load condition in the direction from the low load condition to the high load condition does not occur at least within the time period determined by the timer T2 Transition from NPM mode (state 306) to LPM mode (state 302).

[0038] Sum up image 3 If a low load condition exists or occurs after the timer T2 has expired (event 318), the switch controller 226 can transition from the state 306 to the state 302 (LPM mode). The conversion may include asserting the signal enter_LPM to set the operation of the buck regulator 200 to the LPM mode.

[0039] Figure 4 Shown are similar to those used to transition from state 302 to state 304 and transition from state 304 to state 406 image 3 The state transition diagram 400 shown in. The state transition diagram 400 provides another example of handling over-dynamic load conditions according to some embodiments of the present disclosure. When the buck regulator 200 transitions from the state 304 to the state 406, the transition may include starting a timer T2. As long as the timer T2 is running, the switch controller 226 can remain in the NPM mode (state 406), regardless of any changes in load conditions.

[0040] According to some embodiments, if a high load to low load transition is sensed while the timer T2 is still running (event 416), the timer T2 may be restarted to switch the controller 226 on and off in another period of the timer T2. Maintain the NPM mode (state 406). Since the timer T2 is reset whenever the event 416 occurs, the state transition diagram 400 is only when there is no change in the load condition in the direction from high load to low load for at least the time period determined by the timer T2. It is allowed to switch from NPM mode (state 406) to LPM mode (state 302).

[0041] Sum up Figure 4 If a low load condition exists or occurs after the timer T2 has expired (event 318), the switch controller 226 can transition from the state 406 to the state 302 (LPM mode). The conversion may include asserting the signal enter_LPM to set the operation of the buck regulator 200 to the LPM mode.

[0042] Figure 5 Shows similar to the transition from state 302 to state 304 and transition from state 304 to state 506 image 3 The state transition diagram shown in 500. The state transition diagram 500 provides another example of handling over-dynamic processing load conditions according to some embodiments of the present disclosure. When the buck regulator 200 transitions from the state 304 to the state 506, the transition may include starting a timer T2. The switch controller 226 may remain in the NPM mode (state 306).

[0043] However, if the transition from low load to high load is sensed while the timer T2 is still running (event 516), the transition controller 226 can transition from state 506 to state 502, which is a wait for the expiration of timer T2 Status (event 512). When the timer T2 expires in the state 502, the switch controller 226 may transition back to the state 506 and restart the timer T2.

[0044] Sum up Figure 5 If a low load condition exists or occurs after the timer T2 has expired (event 318) in the state 506, the switch controller 226 may transition to the state 302 (LPM mode). The conversion may include asserting the signal enter_LPM to set the operation of the buck regulator 200 to the LPM mode.

[0045] Image 6 An illustrative embodiment of the switch controller 226 according to some embodiments is shown. The switch controller 226 may include a finite state machine ("state machine") 602 and control logic 604. The state machine 602 can use timers 612, 614. In various embodiments, the state machine 602 may be implemented in Figure 3-Figure 5 The state transition diagram shown in. The state machine 602 may output the mode signal 606 to indicate the NPM mode or the LPM mode. The state machine 602 represents an example of a device for changing the operation of the buck regulator between the NPM mode and the LPM mode. Mode signal 606 represents Figure 3-Figure 5 The exit_LPM signal and enter_LPM signal shown in the state transition diagram.

[0046] The control logic 604 may generate a switch signal 216 to control the operation of the power switches M1, M2. The control logic 604 represents an example of a device for operating the buck regulator 200 in the NPM mode or the LPM mode according to the mode signal 606. For example, the control logic 604 may include logic configured to perform pulse omission to provide operation in the LPM mode. The logic can be enabled (LPM mode) or disabled (NPM mode) according to the mode signal 606.

[0047] reference Figure 3-Figure 5 The discussion of state transition diagrams. In some embodiments, it can be based on the load current I load To determine the step-down regulator 200 ( figure 2 ) The load condition at the output 210. For example, if the load current I load Less than the threshold Th low , It can indicate a low load condition, and if the load current I load Greater than threshold Th high , It can indicate high load conditions. In some embodiments, Th high And Th low There may be a gap between; for example, Th high =Th low +Δ hysteresis. Th high And Th low The gap between Δ hysteresis Can avoid the load current I load Misjudgment of high load and low load conditions caused by spurious artifacts.

[0048] In some embodiments, the state machine 602 may use the current sensing signal 244 to determine the output 210 (e.g., figure 2 The change of the load condition at) between the low load condition and the high load condition. As explained above, the current sensing signal 244 may represent the load current I into the load 22 load. The hysteresis comparator 228 may compare the current sensing signal 244 with a threshold Th (eg, stored in the memory 252) to assert or de-assert the load signal 628, which respectively indicates that a transition from low load to high load has occurred, or A high load to low load transition has occurred.

[0049] In some embodiments, for example, the threshold Th may represent the low load threshold Th low. Therefore, the hysteresis comparator 628 may be configured to de-assert the load signal 628 (low load condition) when the current sensing signal 244 drops below the threshold Th. Conversely, the hysteresis comparator 628 can be configured to when the current sensing signal 244 rises above the value (Th+Δ hysteresis =Th high ), assert the load signal 628 (high load condition), where Δ hysteresis It is the hysteresis of the hysteresis comparator 228.

[0050] In other embodiments, the threshold Th may represent the high load threshold Th high. Therefore, the hysteresis comparator 228 may be configured to assert the load signal 628 (high load condition) when the current sense signal 244 rises above the threshold Th. Conversely, the hysteresis comparator 228 can be configured to act as the load current I load Drops below the value (Th-Δ hysteresis =Th low ) Cancel the assertion of the load signal 628 (low load condition), where Δ hysteresis It is the hysteresis of the hysteresis comparator 228.

[0051] State machine 602 can use timers 612 and 614 as Figure 3-Figure 5 The corresponding timers T1 and T2 are shown in the state transition diagram. In some embodiments, the timers 612, 614 may be counters or other suitable clock-based logic. In other embodiments, the timers 612, 614 may be timer-based logic. The timer values ​​of the timers 612, 614 may be programmable. For example, the timer value may be stored in the memory 252 and read in by the state machine 602. The state machine 602 can generate enable signals 612a, 614a to start the corresponding timers 612, 614, including providing the timers 612, 614 with their respective timer values. The state machine 602 can generate clear signals 612b, 614b to stop the timers 612, 614, for example, according to image 3 with Figure 4 To restart the timers 612, 614 in the state transition diagram in the. The timers 612, 614 may be configured to assert the respective timer completion signals 612c, 614c when the completion of the timer expires.

[0052] Figure 7 A timing diagram is shown to illustrate the basis Figure 3-Figure 5 The state transition diagram in to handle different examples of load conditions. The top trace load profile 702 represents the output 210 of the buck voltage regulator 200 ( figure 2 ) Load current I over a period of time load Example. The load profile 702 includes a high load threshold Th representing a high load condition and a low load condition, respectively high And low load threshold Th low. When the load current is less than Th low Change to greater than Th high 时,在such as t 0 , T 4 And t 6 Triggers or otherwise indicates the transition from low load to high load (low to high); for example, the load signal 628( Image 6 ) Can be asserted. Similarly, when the load current is never greater than Th high Change to less than Th low 时,在such as t 1 , T 5 And t 7 The time of triggers or otherwise indicates a high load to low load (high to low) transition; for example, the load signal 628 may be de-asserted.

[0053] In some embodiments, the threshold Th high , Th low Can include hysteresis. reference Figure 7 Load profile 702 in, for example, at time t a , T b , T c And t d The load current transition in the pulse that occurs does not trigger an indication of the transition of the load condition. For example, at time t a , T b And t d The load current transition in the pulse that occurs will not trigger the transition from low to high because the pulse will not change from less than Th row Span greater than Th high; Therefore, the load signal 628 remains de-asserted. Similarly, at time t c The load current transition in the pulse at the position does not trigger the transition from high to low, because the pulse does not change from greater than Th high Span to less than Th low; Therefore, the load signal 628 remains asserted.

[0054] Traces 712, 714, and 716 represent the transition diagram 300 ( image 3 ), 400( Figure 4 ), 500( Figure 5 ) The mode signal 606 of the state machine 602 ( Image 6 ) Example. For example, the LPM operation mode may be indicated by the deassertion mode signal 606, and the NPM operation mode may be indicated by the assertion mode signal 606. To keep the timing diagram simple, the traces 712, 714, and 716 omit the intermediate transition state 304 shown in the state transition diagrams 300, 400, 500.

[0055] Trace 712 represents the basis image 3 The state transition diagram 300 shown in the operation of the state machine 602. For example, the load profile 702 shows a low to high transition at time t0. Therefore, the trace 712 shows that the mode signal 606 is asserted (NPM mode), and the timer T2 is started at time t0. According to the state transition diagram 300, the state machine 602 does not respond to a high-to-low transition while the timer T2 is running, thereby allowing, for example, the timer T2 to expire at time t2. Moreover, at time t 2 , The mode signal 606 is de-asserted in response to the low load condition; the load profile 702 shows that the load is less than Th low.

[0056] By comparison, at time t 6 , The load profile 702 shows a transition from low to high. Trace 712 shows that in response to the low-to-high transition that occurred while timer T2 was running, the state machine 606 operating according to the state transition diagram 300 at time t 6 Restart timer T2. Timer T2 at time t 8 Due, and due to the load profile 702 at time t 8 A low load condition is shown, so the mode signal 606 is de-asserted (LPM mode).

[0057] It is worth noting that as time t a And time t b The low-to-high transition occurs due to the pulse. This low-to-high transition will not trigger the restart of timer T2, because the transition will not become greater than the high load threshold Th high.

[0058] Trace 714 indicates that according to Figure 4 The state transition diagram 400 is shown in the operation of the state machine 602. For example, load profile 702 shows a low-to-high transition at time t0, which starts timer T2. Trace 714 shows that the state machine 606 operating according to the state transition diagram 400 at time t due to the high-to-low transition that occurred while the timer T2 was running 1 Restart timer T2 at any time. When the timer T2 is at t 3 When it expires, because at time t 3 In the presence of a low load condition, the mode signal 606 is de-asserted (LPM mode).

[0059] It is worth noting that at time t 5 High to low transition in the initial load profile 702. Trace 714 shows that timer T2 is at time t 5 And t 7 It is restarted twice because the high-to-low transition occurs while the timer T2 is running. Another notable transition is at time t c The high-to-low transition of the pulse. Since the load profile shows the load current I load Not below the low load threshold Th low , So the transition does not trigger the restart of timer T2.

[0060] Trace 716 indicates that according to Figure 5 The state transition diagram 500 is shown in the operation of the state machine 602. For example, the load profile 702 shows that at time t 4 The transition from low to high starts timer T2. According to the state transition diagram 500, the state machine 602 ignores that at time t 5 The conversion from high to low. However, at time t 6 The transition from low to high causes the state machine 602 to wait for the timer T2 to expire, and when the timer T2 expires, it is restarted.

[0061] The foregoing description illustrates various embodiments of the present disclosure and examples of how aspects of specific embodiments may be implemented. The above examples should not be considered the only embodiments, and are presented to illustrate the flexibility and advantages of the specific embodiments defined by the appended claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations, and equivalents may be adopted without departing from the scope of the present disclosure as defined by the claims.