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A multi-level flash memory unit error correction method, system, device and readable storage medium

A technology of flash memory unit and error correction method, applied in the field of flash memory, can solve the problems of LDPC error correction code error correction performance degradation, logarithm is no longer accurate, etc., to achieve the effect of ensuring reliability and error correction performance

Active Publication Date: 2020-07-10
SLICONGO MICROELECTRONICS INC
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Problems solved by technology

However, the persistent interference of flash memory increases with the increase of erasing and programming times and data retention time, and the log likelihood ratio of the original storage is no longer accurate, which leads to the error correction performance of LDPC error correction codes decreasing gradually

Method used

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  • A multi-level flash memory unit error correction method, system, device and readable storage medium
  • A multi-level flash memory unit error correction method, system, device and readable storage medium
  • A multi-level flash memory unit error correction method, system, device and readable storage medium

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Embodiment Construction

[0039]The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0040] The embodiment of the present invention discloses a multi-level flash memory unit error correction method, see figure 1 As shown, the method includes:

[0041] Step S11: Using the threshold voltage probability density function of inter-unit interference to calculate the average value of the threshold voltage distribution of each threshold voltage window after the inter-unit interference.

[0042] It can be understood that flash memory is composed of mul...

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Abstract

The invention discloses a multistage flash memory unit error correction method, a system, a device and a readable storage medium. The multistage flash memory unit error correction method comprises thesteps: utilizing an inter-cell interference threshold voltage probability density function to calculate out a cell threshold voltage distribution mean value of all threshold voltage windows after inter-cell interference; then calculating out a threshold voltage distribution mean value and a standard deviation of all the threshold voltage windows after inter-cell interference and durable interference; calculating out a reference voltage deviation value among all the threshold voltage windows and utilizing the reference voltage deviation value among all the threshold voltage windows to adjust reference voltage among all the threshold voltage windows in an error correction code coder. According to the multistage flash memory unit error correction method disclosed by the invention, effects ofthe inter-cell interference and the durable interference to the flash memory is comprehensively taken into consideration, the threshold voltage distribution mean value and the standard deviation of flash memory after the inter-cell interference and the durable interference are utilized to calculate out reference voltage which can be dynamically adjusted according to erasure, programming and timechange, LDPC error correction codes of the flash memory can well ensure reliability of flash memory, and error correction performance of the error correction codes can be ensured.

Description

technical field [0001] The invention relates to the field of flash memory, in particular to a multi-level flash memory unit error correction method, system, device and readable storage medium. Background technique [0002] With the development of technology, NAND flash memory has attracted more and more attention because of its shock resistance, fast read and write, etc., which makes flash memory have greater storage density and reduce costs. However, the increase in flash memory density also increases the internal interference of flash memory, which affects its reliability. With the application of MLC (Multi-Level Cell, multi-level cell flash memory) and TLC NAND flash memory, the internal interference of flash memory increases. , the traditional BCH error correction code can no longer guarantee the reliability of flash memory. Because the flash memory needs to have high reliability as a storage element. Generally in flash memory, the bit error rate needs to reach 10 -15...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/34G11C29/42
CPCG11C16/3404G11C29/42
Inventor 韩国军刘文杰何瑞泉方毅
Owner SLICONGO MICROELECTRONICS INC
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