Parallel implementation method of sub-pixel motion estimation

A technology of motion estimation and implementation method, applied in image communication, digital video signal modification, electrical components, etc., can solve the problems of long time consumption and high complexity of motion estimation process, reduce search time, reduce computational complexity, and speed up frames The effect of inter-pixel motion estimation

Inactive Publication Date: 2018-07-06
TIANJIN UNIV
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Problems solved by technology

Due to the large number of PUs that can be divided into each largest coding unit in...

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  • Parallel implementation method of sub-pixel motion estimation
  • Parallel implementation method of sub-pixel motion estimation
  • Parallel implementation method of sub-pixel motion estimation

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Embodiment Construction

[0032] A parallel implementation method of sub-pixel motion estimation of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.

[0033] Such as image 3 As shown, a parallel implementation method of sub-pixel motion estimation of the present invention includes the following steps:

[0034] 1) Set the size of the thread grid and thread block in the CUDA platform kernel function;

[0035] 2) Start the CUDA platform sub-pixel motion estimation kernel function;

[0036] 3) Allocate shared memory for the current largest coding unit on the device side, including coding unit pixel value cache, sub-block SATD value storage, PU motion vector storage, and PU motion vector cost storage;

[0037] 4) Read the pixel value of the current largest coding unit from the texture memory into the pixel value cache of the coding unit in the shared memory in parallel, and initialize the relevant parameters of the current largest co...

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Abstract

A parallel implementation method of sub-pixel motion estimation comprises the steps of: setting the size of a thread grid and a thread block in the kernel function of a CUDA platform; starting the sub-pixel motion estimation kernel function of the CUDA platform; allocating a shared memory for the current maximum coding unit on a device terminal; initializing a motion vector and a motion vector cost of each PU; determining the number of modes divided by the PU; determining, according to the search result of the integer pixel motion estimation, a center search point of all PUs of the current maximum coding unit at a reference frame; performing a 1/2 pixel refinement search for each PU near the current center search point; performing a 1/4 pixel refinement search for each PU near the currentcenter search point, and recording the search result to the motion vector storage of the PU and the motion vector cost storage of the PU in the shared memory; determining whether all the modes are traversed; and copying the motion vector of each PU and the motion vector cost of each PU in the current maximum coding unit into a global memory. The invention is capable of effectively accelerating theinter-frame sub-pixel motion estimation.

Description

technical field [0001] The invention relates to a sub-pixel motion estimation method. In particular, it relates to a parallel implementation method of sub-pixel motion estimation. Background technique [0002] With the emergence of high-resolution video, its requirements for video information compression are getting higher and higher. The emergence of a new generation of video coding standard AVS2 has greatly eased this challenge. AVS2 is the second-generation digital audio and video coding standard with my country's independent intellectual property rights. AVS2 has surpassed the traditional video coding standard AVS1 in terms of compression quality and efficiency by introducing multiple innovative coding technologies. [0003] In order to improve the flexibility and accuracy of prediction, AVS2 adopts the quadtree division structure, and the block division is more flexible. It is mainly divided into coding unit (Coding Unit, CU), prediction unit (Prediction Unit, PU) a...

Claims

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Application Information

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IPC IPC(8): H04N19/436H04N19/51H04N19/96
CPCH04N19/436H04N19/51H04N19/96
Inventor 张涛安鑫祺赵鑫
Owner TIANJIN UNIV
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