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Junction field effect transistor and method of manufacturing the same

A technology of field effect transistor and manufacturing method, applied in the field of junction field effect transistor and its manufacturing, capable of solving problems such as weak anti-static discharge ESD ability

Active Publication Date: 2020-09-04
CSMC TECH FAB2 CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, for the application environment of high-voltage Junction Field-Effect Transistor (JFET), no external electrostatic discharge protection device or circuit is allowed to protect, and the traditional Junction Field-Effect Transistor’s ability to resist electrostatic discharge ESD is relatively weak

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  • Junction field effect transistor and method of manufacturing the same
  • Junction field effect transistor and method of manufacturing the same
  • Junction field effect transistor and method of manufacturing the same

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Embodiment Construction

[0033] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the associated drawings. Preferred embodiments of the invention are shown in the accompanying drawings. However, the present invention can be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of ...

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Abstract

A junction field-effect transistor and a fabricating method thereof. The junction field-effect transistor comprises a substrate (100), and an epitaxial layer (200) and a dielectric mask layer sequentially arranged on the substrate. A first conductive type well region (210) is arranged in the epitaxial layer (200). A drain region (213) and a source region (211) are arranged in the first conduction type well region (210). The dielectric mask layer is used to define the source region (211) and the drain region (213). The dielectric mask layer corresponding to the drain region (213) comprises a plurality of separate mask sub-units separating the drain region into a plurality of separated drain region sub-units (2131). The drain region sub-units (2131) and the mask sub-units are arranged to have a one-to-one correspondence.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a junction field effect transistor and a manufacturing method thereof. Background technique [0002] Electrostatic Discharge (Electrostatic Discharge) refers to the charge transfer caused by objects with different electrostatic potentials approaching or directly contacting each other. During electrostatic discharge, a large current will be generated in a short time, which will cause fatal damage to the integrated circuit, which is an important problem causing failure in the production and application of integrated circuits. For example, the human body model electrostatic discharge (HBM) usually occurs within a few hundred nanoseconds, and the maximum current peak may reach several amperes; while the electrostatic discharge of the machine model (MM) and charged device model (CDM) The time to occur is shorter and the current is greater. Such a large current passes through ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/808H01L21/337
CPCH01L29/66227H01L29/808H01L29/78
Inventor 林中瑀
Owner CSMC TECH FAB2 CO LTD