FPGA-based TDC realization method

Abstract

Te invention provides an FPGA-based time-digital conversion (TDC) realization method. By using a digital clock management (DCM) tool of an FPGA, a clock is subjected to phase shift to generate 2 or 4clocks with phase differences of 180 degrees or 90 degrees; the generated clocks are distributed in different clock regions of the FPGA; and a same delay chain program is configured. Through a phase inverter group, the difference of time of reaching each group of delay chains by an input to-be-tested signal does not exceed 1ns. The method has the practical effects that the clock is subjected to frequency doubling, so that the length of the delay chains can be reduced to half or 1/4 of the original length, the delay characteristics of the delay chains are ensured to be consistent, and the problem of differential nonlinearity (DNL) caused by excessively long delay chains is solved.

Description

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AI Technical Summary

Benefits of technology

The technical effect that this invention addresses is how it can improve the accuracy of distance measurement between two objects accurately without causing any problems with longer delays due to factors like temperature or humidity changes over time. This technology could be used also during manufacturing processes where precise measurements are needed quickly and at an affordable cost.

Problems solved by technology

This patents describes how to measure distance accurately from a specific point or range through multiple points simultaneously. Current techniques involve either measuring directly or indirectly via specialized circuits within an ASIC chip. These techniques require expensive equipment and consume considerable amounts of space during operation due to their complexity. Additionally, current solutions only work well over limited ranges where they could provide high precision measurements.

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