Extended instruction execution method and device suitable for short operands for processor

Abstract

The present invention provides an extended instruction execution method applicable to short operands for a processor. The method comprises: 1) extracting an extended instruction, wherein the extendedinstruction is obtained by expanding an original long operand instruction of the processor, the original long operand instruction comprises at least two domains for specifying positions of operands, the operand comprises the source operand and the destination operand, and at least one domain of the original long operand instruction for specifying the operand position is redefined as the domain forspecifying positions of two short operands so as to obtain the extended instruction; 2) decoding the instruction, and decomposing the instruction into a control signal corresponding to a series of micro-operations; and 3) distributing the control signal to address and extract the short operands, to execute the operation corresponding to the original long instruction, and to store the operation result into a register specified by the extended instruction. The present invention also provides an extended instruction execution apparatus applicable to short operands for a processor.

Description

technical field [0001] The invention relates to the technical field of microprocessor architecture, in particular, the invention relates to a method and device for executing extended instructions suitable for short operands for processors. Background technique [0002] With the development of computing technology, in order to meet the needs of various new applications and improve the performance of a certain aspect, many manufacturers have expanded the instruction set. For example, in order to improve the performance of software such as images and multimedia, single instruction multiple data stream instructions are added; for the speed of encryption and decryption, encryption and decryption instructions are added. This expansion of the instruction set has led to a rapid increase in the number of instructions for the processor. For example, the number of instructions of the x86 architecture reached 1300 in 2015; the number of instructions of the ARMv8 architecture reached 10...

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Problems solved by technology

However, this scheme needs to detect or predict the operand width (refer to Ahmadian S N, Fazeli M, Ghalaty N F, etal. Value-Aware low-power register file architecture[C] / / Computer Architecture and Digital Systems (CADS), 2012 16th CSI International Symposium on.IEEE,2012:44-49.), so it is necessary to design a logic unit that detects or predicts the width of the operand, which brings additional overhead

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