SOC chip and method having debugging interface safety mechanism

Abstract

The invention provides an SOC chip and method having a debugging interface safety mechanism. The chip includes a debugging port, a microprocessor, a storage unit and a safety control unit, wherein themicroprocessor includes a debugging interface; the storage unit is used for beforehand storing a debugging interface safety access password; and the safety control unit is connected between the debugging port and the debugging interface, and is used for monitoring the input timing sequence of external equipment connected to the debugging port, an input password is compared with the debugging interface safety access password when the input timing sequence is correct, if the comparison result is consistent, a channel between the debugging port and the debugging interface can be opened, and if the comparison result is not consistent, the channel can be closed. The safety control unit is added between the physical debugging port and the internal debugging interface, isolation can be performedfrom physical connection, the debugging port can physically communicate with the internal debugging interface only when a timing waveform signal containing a correct password is input on the debugging port, and therefore, permissions which can access internal resources can be obtained.

Description

technical field [0001] The invention belongs to the field of on-chip systems, and relates to a SOC chip with a debugging interface security mechanism and a method. Background technique [0002] System on Chip (SOC for short), from a narrow point of view, it is the chip integration of the core of the information system, which integrates the key components of the system on a chip; from a broad point of view, SOC is a micro system, which will Microprocessor, analog IP core, digital IP core and memory (or off-chip storage control interface) are integrated on a single chip, usually customized by customers, or standard products for specific purposes. [0003] The hardware debug interface provides an effective method for system testing and on-chip debugging of SoC chips, but it also causes potential safety hazards. [0004] The current SoC chip will integrate a debugging interface for chip testing and system debugging. Users can easily use the host computer software for applicatio...

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Problems solved by technology

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a SOC chip and method with a debugging interface security mechanism, which is used to solve the problem of high security risks of the SOC chip in the prior art

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