Class-d amplifier
An amplifier and modulator technology, applied in amplifiers, low-frequency amplifiers, amplifier types, etc., can solve the problems of increased loss of output transistors, heat generation, etc.
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no. 1 Embodiment approach
[0028] figure 1 It is a circuit diagram showing the class D amplifier of the first embodiment of the present invention. In addition, figure 2 It is a circuit diagram of a Class D amplifier showing related technology.
[0029] In this embodiment, it is possible to dynamically change the transistor size of the output transistor (switching transistor) used in the power amplification of the D-class amplifier, thereby reducing loss regardless of the input and output levels in actual use.
[0030] First, refer to Figure 2 to Figure 5 The relationship between the transistor size of the output transistor and the loss corresponding to the input level (output level) of the Class D amplifier will be described. image 3 It is a graph showing the relationship between the input audio signal and the triangular wave, the normal phase PWM output PWM+ and the reverse phase PWM output PWM-. Figure 4 It is a graph showing the relationship between transistor size and loss by taking output power on th...
no. 2 Embodiment approach
[0096] Picture 10 It is a circuit diagram showing the second embodiment of the present invention. in Picture 10 In order to simplify the drawing, it is represented by the PWM modulator 50 figure 1 The inverting circuit 11, the carrier generating circuit 12, and the two comparators 13p and 13n are shown as follows. Regarding the subsequent stage of the PWM modulator 50, only the configuration on the positive phase side is shown. In addition, the configuration on the negative side after the dead time generating circuit 14n is the same as the configuration on the positive side after the dead time generating circuit 14p, and illustration and description are omitted.
[0097] In the first embodiment, four output transistors for the high-side and low-side of the positive phase, and four output transistors for the high-side and low-side of the reverse phase, respectively, are used in parallel with two transistors. The same characteristics for both cases. In contrast, in this embodime...
no. 3 Embodiment approach
[0130] Figure 17 It is a circuit diagram showing the third embodiment of the present invention. Figure 17 In order to simplify the drawing, the driver circuit 52 represents the Picture 10 The dead time generating circuit 14p, the level shift circuit 40p, and the selectors 41pH and 41pL have the same configuration. The selectors 41pH and 41pL output PWM pulses from the OUT1 and OUT2 terminals. In contrast, the driver circuit 52 can output PWM pulses from the output terminals of the m system.
[0131] In the second embodiment, each output transistor is configured by three transistors connected in parallel, and the number of parallel connections of transistors to be driven is controlled, so that the gate width of the transistor can be changed. In contrast, in the present embodiment, each output transistor is configured by m transistors connected in parallel, and the number of parallel connected transistors to be driven is controlled, so that the transistor size can be finely contr...
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