Gate driver monolithic
A driving circuit, gate scanning technology, applied in the direction of instruments, static indicators, etc., can solve the problems of reducing circuit reliability, instability, increasing circuit complexity, etc., to avoid circuit failure and narrow the frame effect.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0096] Such as Figure 7 Shown is a circuit diagram of the first embodiment of a gate scan driving circuit. The nth-level driving circuit unit includes a positive and negative scan control module 01, a pull-up module 02, a touch auxiliary module 03, a maintenance auxiliary module 04, and a memory compensation module 05 and the first capacitor C1. Positive and negative scanning control module 01, pull-up module 02, maintenance auxiliary module 04, and memory compensation module 05 are connected to the pull-up control node netAn; positive and negative scanning control module 01, touch auxiliary module 03 and maintenance auxiliary module 04 all input constant The low level VSS is pressed; the pull-up module 02 and the touch assistant module 03 are connected to the gate scanning signal line of this level, and the gate scanning signal line outputs the gate scanning signal Gn; the first capacitor C1 is connected to the pull-up control node netAn and Between the gate scan signal lines...
Embodiment 2
[0133] Picture 9 It is a schematic circuit diagram of Embodiment 2 of a gate scan driving circuit of the present invention. The second embodiment is improved on the basis of the first embodiment, and the specific improvements are as follows:
[0134] 1. The memory compensation module 05 of the n-th drive circuit unit also includes a sixteenth thin film transistor M9B, the control terminal of the sixteenth thin film transistor M9B inputs the second clock signal CKm+4, and the two paths of the sixteenth thin film transistor M9B The terminals are respectively connected to the pull-up control node netAn and the input constant voltage low level VSS; the sixteenth thin film transistor M9B is responsible for clearing and resetting the memory compensation node netCn in time to ensure that the memory compensation node netCn can be synchronized with the pull-up control node netAn;
[0135] 2. The control end of the fourth thin film transistor M4 in the memory compensation module 05 is conne...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


