Wafer chip testing method
A testing method and chip testing technology, applied in electronic circuit testing, single semiconductor device testing, electrical measurement, etc., can solve problems such as inability to effectively detect chip optical parameters
Active Publication Date: 2018-10-23
MAANSHAN JASON SEMICON CO LTD
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Problems solved by technology
[0005] The invention provides a method for testing wafer chips, which solves the problem that the existing wafer chips of flip chip, vertical chip and ultraviolet chip type cannot effectively detect the real optical parameters of the chip
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[0044] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention , but not all examples. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
[0045] figure 1 Test schematics for existing wafer chips. Such as figure 1 As shown, the middle part of the stage 004 where the wafer is placed is hollowed out, or it is set as a light-transmitting stage.
[0046] The LED wafer 002 to be tested is vacuum-adsorbed or mechanically locked on the stage.
[0047] The probe 001 and the optical detection device 003 of the test devi...
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The invention provides a wafer chip testing method. The method includes the following steps: performing full-scale testing of a first wafer chip to obtain first test data, wherein the first wafer chipis located on a non-thinned and non-cut wafer, and the wafer can be cut into a plurality of first wafer chips; performing full-scale testing of a second wafer chip to obtain second test data, whereinthe second wafer chip is obtained after the thinning and cutting of the first wafer chip; merging the first test data of the first wafer chip and the second test data of the corresponding second wafer chip to obtain third test data. According to the wafer chip testing method provided by the invention, the electrical data in the third test data is derived from the second electrical data in the second test data, and can truly represent the yield condition after the wafer is cut. The optical data in the third test data is derived from the optical data of the first test data, and solves a problemthat the true optical parameters of the wafer chip cannot be detected.
Description
technical field [0001] The invention relates to the technical field of chip testing and sorting, in particular to a wafer chip testing method. Background technique [0002] In the semi-finished state of the chip, that is, the state of the wafer without thinning and cutting (wafer without thinning and cutting: ChipOn Wafer), the semi-finished chip on each chip will be tested, and the photoelectric parameters will be used to determine whether the chip has The value of further processing. The test of semi-finished products can be a random test or a full test. For example, usually a random test refers to taking a certain number of chips from a single chip according to a certain ratio for testing, and counting whether the photoelectric parameters on it meet the preset standards and whether the yield level is up to standard. . The sampling yield can represent the overall yield level of the wafer to a certain extent. Unthinned and diced wafers that meet this yield requirement ar...
Claims
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IPC IPC(8): G01R31/26G01R31/28
CPCG01R31/2601G01R31/2851
Inventor 姚禹郑远志陈向东梁旭东
Owner MAANSHAN JASON SEMICON CO LTD