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Depthwise separable convolutional neural network processing architecture/method/system and medium

A convolutional neural network and deep convolution technology, applied in the field of deep separable convolutional neural network processing architecture, processing architecture, can solve the problem of massive data calculation and transmission, consumption of power consumption and data bandwidth, and failure to achieve energy consumption Excellent problems, achieve resource consumption and power consumption balance, increase calculation speed, improve data bandwidth and system operation performance

Active Publication Date: 2022-07-05
SHANGHAI ADVANCED RES INST CHINESE ACADEMY OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a convolutional neural network processing architecture / method / system and medium, which is used to solve the problem of requiring a large amount of data calculation and processing when running a deep neural network in the prior art. Transmission, its frequent off-chip and on-chip data transmission causes a lot of energy consumption, and the off-chip access of intermediate calculation results and output data also consumes a lot of power consumption and data bandwidth, which cannot achieve optimal energy consumption , leading to problems that limit applications in low-power, low-latency, high-performance mobile edge computing scenarios

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  • Depthwise separable convolutional neural network processing architecture/method/system and medium

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Embodiment 1

[0069] This embodiment provides a depthwise separable convolutional neural network processing architecture, including:

[0070] an on-chip buffer for buffering the input eigenvalues ​​of the convolutional neural network, and the input eigenvalues ​​one by one, read from the off-chip memory of the processing architecture of the depthwise separable convolutional neural network through the host interface and direct memory access Corresponding depth convolution weight value and point-by-point convolution weight value;

[0071] At least one depthwise separable convolution operation engine is in communication connection with the on-chip buffer, and is used for performing depthwise convolution operation on the depthwise separable convolutional neural network to generate an output value of the depthwise convolution; The output value of the depthwise convolution is subjected to a pointwise convolution operation to generate the output value of the pointwise convolution.

[0072] The pr...

Embodiment 2

[0103] This embodiment provides a depthwise separable convolutional neural network processing method, including:

[0104] performing a depthwise convolution operation on the depthwise separable convolutional neural network to generate an output value of the depthwise convolution;

[0105] A pointwise convolution operation is performed on the output value of the depthwise convolution to generate the output value of the pointwise convolution.

[0106] The processing method of the depthwise separable convolutional neural network provided by this embodiment will be described in detail below with reference to the drawings. see Figure 5 , shown as a schematic flowchart of a processing method of a depthwise separable convolutional neural network in an embodiment. like Figure 5 As shown, the processing method of the convolutional neural network specifically includes the following steps:

[0107] S51, read the input feature value of the depthwise separable convolutional neural ne...

Embodiment 3

[0116] This embodiment provides a processing system for a depthwise separable convolutional neural network, including:

[0117] a depthwise convolution module for performing a depthwise convolution operation on the depthwise separable convolutional neural network to generate an output value of the depthwise convolution;

[0118] The point-by-point convolution module is used to perform a point-by-point convolution operation on the output value of the depthwise convolution to generate the output value of the point-by-point convolution.

[0119]The processing system of the depthwise separable convolutional neural network provided by this embodiment will be described in detail below with reference to the drawings. It should be noted that, it should be understood that the following division of each module of the processing system is only a division of logical functions, and in actual implementation, it may be fully or partially integrated into a physical entity, or may be physicall...

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Abstract

The present invention provides a depth separable convolutional neural network processing architecture / method / system and medium, the processing architecture includes: an on-chip buffer for buffering a processing device from a depthwise separable convolutional neural network accessed through a host interface and direct memory The input eigenvalue of the depthwise separable convolutional neural network, the depthwise convolutional weight value and the point-by-point convolutional weight value corresponding to the input eigenvalue one-to-one read from the off-chip memory; at least one depthwise separable convolution operation engine , which is used to perform the depthwise convolution operation on the depthwise separable convolutional neural network to generate the output value of the depthwise convolution; and is used to perform the pointwise convolution operation on the output value of the depthwise convolution to generate the output value of the pointwise convolution . Aiming at the parallel characteristics of the depthwise separable convolutional neural network, the present invention focuses on the hardware optimization design of the depthwise convolution and point-by-point convolution in the convolutional layer, and achieves a balance in speed, resource consumption and power consumption, and improves the calculation speed. , reducing the system running delay.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit processor chip architecture and circuit design, and relates to a processing architecture, method and system, in particular to a depth separable convolutional neural network processing architecture / method / system and medium. Background technique [0002] Artificial intelligence represented by artificial neural networks has achieved rapid development in recent years, and it has been widely used in many fields such as security, autonomous driving, drones, smart speakers, medical imaging and consumer electronics. All countries also attach great importance to the development of artificial intelligence technology, and academia and industry have invested a lot of manpower and material resources in technology research and development and product implementation. Convolutional neural network is the most common and widely used artificial neural network algorithm model, which has the characteristics...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06N3/04G06N3/063
CPCG06N3/063G06N3/045Y02D10/00
Inventor 汪辉丁伟祝永新田犁黄尊恺
Owner SHANGHAI ADVANCED RES INST CHINESE ACADEMY OF SCI