Display substrate, driving method thereof and display device
A technology for displaying substrates and clock signals, applied to static indicators, instruments, etc., can solve the problems of limiting the frame size of the display panel, the display panel frame cannot be reduced, and the size of the steps is large, so as to achieve small frames, reduce the number, and reduce wiring Effect
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0054] See Figure 5 , Figure 5 is a schematic circuit diagram of a display substrate when N is 2, wherein, Figure 5 In the figure, three control modules are taken as an example, but it should be known that in practical applications, the display substrate may also include more control modules, and the number of control modules is not limited in this embodiment of the present invention.
[0055] Specifically, the display substrate includes a reference signal line VGL and a clock signal line group CK. Wherein, the clock signal line group CK may include a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line, and the first clock signal line and the second clock signal line may form a pair of clock signal lines line, the third clock signal line and the fourth clock signal line may form a pair of clock signal lines. Wherein, each clock signal line is connected with a clock signal generator VCK, that is, the first clock si...
Embodiment 2
[0078] See Figure 8 , Figure 8 is a schematic circuit diagram of a display substrate when N is 3, wherein, Figure 8 In the figure, two control modules are taken as an example, but it should be known that in practical applications, the display substrate may also include more control modules, and the number of control modules is not limited in this embodiment of the present invention.
[0079] Specifically, the display substrate includes a reference signal line VGL and a clock signal line group CK. Wherein, the clock signal line group CK may include a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line and a sixth clock signal line, the first clock signal line and The second clock signal line can form a pair of clock signal lines, the third clock signal line and the fourth clock signal line can form a pair of clock signal lines, and the fifth clock signal line and the sixth clock signal line c...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


