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Overlapping precharge and data write

A pre-charging, pre-charging circuit technology, applied in the direction of electrical digital data processing, digital memory information, instruments, etc.

Active Publication Date: 2019-03-01
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] With the ever-increasing demand for more processing power, a design challenge is to improve the performance of PDP memory

Method used

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  • Overlapping precharge and data write
  • Overlapping precharge and data write
  • Overlapping precharge and data write

Examples

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Embodiment Construction

[0022] The detailed description set forth below in connection with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring the concepts. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other designs.

[0023] Several aspects of the disclosure will now be presented with reference to various apparatus and methods. These de...

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Abstract

A memory and a method for operating the memory are presented. The memory includes a plurality of memory cells and a plurality of bitlines. Each of the plurality of bitlines is coupled to a corresponding one of the plurality of memory cells. A precharge circuit precharges each of the plurality of bitlines before a read operation and precharges all but one of the plurality of bitlines following theread operation. A write driver drives the one of the plurality of bitlines following the read operation. The method includes precharging each of a plurality of bitlines before a read operation. Each of the plurality of bitlines is coupled to a corresponding one of a plurality of memory cells. The method further includes precharging all but one of the plurality of bitlines following the read operation and driving the one of the plurality of bitlines following the read operation.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of US Patent Application No. 15 / 205,857, filed July 8, 2016, entitled "OVERLAPPING PRECHARGE AND DATAWRITE," which is expressly incorporated herein by reference in its entirety. technical field [0003] The present disclosure relates generally to memory circuits, and more particularly to memories with improved precharging and data writing schemes. Background technique [0004] Memory is an important component for wireless communication devices (eg, integrated as part of the application processor in a cell phone). Many wireless applications rely on the capability of dual-port memories (eg, memories that can handle both read and write operations in a single clock cycle). Dual-port memories typically include two ports that operate with an array of memory cells that can be accessed simultaneously from the two ports. For example, a dual-port memory can access two different memory locat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/12
CPCG11C7/08G11C7/1075G11C2207/002G11C2207/2209G11C7/12G11C11/419G06F12/00G11C7/06
Inventor S·戈什晶昌镐
Owner QUALCOMM INC