A DRC processing method for deleting Net metal wires

Abstract

The invention provides a DRC processing method for deleting Net metal connection lines, which comprises the following steps: step 1, establishing a circuit node type to which a corresponding Net belongs based on information of the Net with a DRC error obtained by DRC, and then entering a step 2; 2, extracting the Net of which the circuit node type is a signal in the step 1, and then entering the step 3; Step 3, deleting the metal connection line of any Net extracted in the step 2, and then entering the step 4; 4, automatic wiring is executed again, and then the step 5 is executed; and 5, judging whether a DRC error exists or not by executing DRC inspection, if yes, returning to the step 1, and otherwise, ending. The whole process is automatically completed by tools, and both hands of a designer are liberated.

Description

technical field [0001] The invention relates to the field of integrated circuit layout automation design, in particular to a DRC processing method for deleting Net metal connections. Background technique [0002] In the use of EDA tools to complete the digital chip back-end layout design process, one of the important factors is the routing rate of the chip, which directly affects the success or failure of a chip. The direct performance of the routing rate of the chip is DRC problems such as short circuit and distance requirements between adjacent connections. Therefore, when there is a DRC problem in the design, it is necessary to focus on solving this problem. Currently, the way to solve this problem is as follows: [0003] The location information where the DRC occurs is obtained through the EDA tool. Designers often manually delete the connections near the location where the DRC error occurs, and then let the EDA tool re-execute the wiring operation. The manual method ...

AI Technical Summary

Problems solved by technology

However, the manual method has many disadvantages.

1. Manual operation takes a lot of time to complete, which reduces wiring efficiency; 2. There are a large number of repeated operations, especially when the amount of layout data is large, the entire process takes too long and is prone to misoperation; 3. Designers Always pay attention to this operation and cannot leave; 4. If the manually deleted connection includes the clock connection, it is likely to reduce the performance of the chip, and even more seriously, it may affect the function of the chip and cause the failure of the chip

[0004] The whole operation process is time-consuming and labor-intensive, and may cause DRC (Design Rule Check, design rule check) or LVS (Layout Versus Schematics, layout and schematic consistency check) verification errors due to human error; there are also problems affecting the chip. Performance and function factors greatly limit the efficiency of chip design, which leads to delayed chip tape-out, delayed time to market, and reduced chip competitiveness.

Images