Implementation method of a fault-tolerant logic H gate based on an RMQC code

A technology of fault-tolerant logic and implementation method, which is applied in the field of quantum computing and quantum error-correcting codes, and can solve the problems of not considering single qubit, fault-tolerant logic H-gate implementation process, high resource consumption, etc.

Active Publication Date: 2019-05-17
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The purpose of the present invention is to overcome the defects of the above-mentioned prior art, and proposes a method for implementing a fault-tolerant logic H gate based on RMQC codes, in order to solve the fault-tole

Method used

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  • Implementation method of a fault-tolerant logic H gate based on an RMQC code
  • Implementation method of a fault-tolerant logic H gate based on an RMQC code
  • Implementation method of a fault-tolerant logic H gate based on an RMQC code

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Example Embodiment

[0044] Example 1:

[0045] This embodiment is used in the coded state |Ψ> RMQC(4) The fault-tolerant logic H gate is implemented on it.

[0046] Reference figure 1 , The present invention includes the following steps:

[0047] Step 1) For the encoded state |Ψ> RMQC(4) Add H gate to each qubit:

[0048] The pair contains three stable subgroups with The encoded state|Ψ> RMQC(4) The 15 qubits in the qubits are respectively numbered and added H gate to obtain the intermediate state Where |Ψ> RMQC(4) The number of stable sons included is 14, which are Contains the 4 X stabilizers, 4 Z stabilizers included, and 6 Z stabilizers included;

[0049] Step 2) Obtain three stable subgroups with The symptom value corresponding to each stable sub:

[0050] Step 2a) Yes Z stabilizer and Measure the X stable sub in, and get the symptom value corresponding to each Z stable sub Symptom value corresponding to each X stable sub i∈{1,2,...,6}, j∈{1,2,...,4}, Get symptom value for:

[0051] ...

Example Embodiment

[0092] Example 2:

[0093] This embodiment is the same as step 1) to step 4) and step 7) to step 8) in embodiment 1, except that step 5) and step 6) are modified to be used in the coded state |Ψ> RMQC(5) The fault-tolerant logic H gate is implemented on it.

[0094] Reference figure 1 ,

[0095] Step 5) Yes All contained Z stable subgroups are grouped:

[0096] Each x-model contained in the 5-model is composed of two vertices of the inner model and the outer model. Z stabilizer Combined into bilateral stable subgroups x∈{4,5}, index∈{1,2,...,(x-1)×2 5-x }, the bilaterally stable subgroups corresponding to all x-models Combine into a set of bilateral stable subgroups among them:

[0097]

[0098]

[0099] among them:

[0100]

[0101]

[0102]

[0103]

[0104] At the same time, divide each x-model contained in the 5-model Outside belong Z stabilizer Combine into single-sided stable subgroups One-sided stable subgroups corresponding to all x-models Combine into a single-side...

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Abstract

The invention provides an implementation method of a fault-tolerant logic H gate based on an RMQC code, and solves the problems of non-fault tolerance caused by the fact that a single quantum bit error is not considered and large resource consumption caused by repeated measurement of a stabilizer. The method comprises the following implementation steps: adding an H gate to a coded state to obtainan intermediate state; measuring the stabilizers to obtain symptom values; according to the symptom value, obtaining the type and position of a single quantum bit error; establishing a graph model ofthe RMQC code; Performing geometric classification on the stabilizers; grouping the stabilizers according to the geometric types of the stabilizers and determining repair operators corresponding to the stabilizers; correcting the symptom value according to the single quantum bit error, and determining a repair operator for repairing the intermediate state according to the corrected symptom value;and then adding the repair operator and the single quantum bit error to the intermediate state. The method has the advantages of fault tolerance and high resource utilization rate, and can be used forrealizing the fault-tolerant general logic gate set in the quantum computer.

Description

technical field [0001] The invention belongs to the technical field of quantum computing and quantum error correction codes, and relates to a method for realizing a fault-tolerant logic H gate, in particular to a method for realizing a fault-tolerant logic H gate based on RMQC codes, which can be applied to fault-tolerant general logic gates in quantum computers realization of the set. Background technique [0002] Quantum computing has attracted the attention of people from all walks of life because of its potential powerful computing power. Its essence is to use quantum coherence to complete quantum computing. However, in practical applications, maintaining this state of quantum coherence is very difficult. Therefore, in order to realize quantum computing, a key issue is to overcome the phenomenon of quantum decoherence. Coding qubits is one of the effective ways to solve this problem, so people have invested a lot of energy in quantum error-correcting codes. However, t...

Claims

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Application Information

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IPC IPC(8): H03M13/13
Inventor 权东晓牛力朱莉莉朱畅华赵楠易运晖何先灯陈南
Owner XIDIAN UNIV
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