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Implementation method of fault-tolerant logic h-gate based on rmqc code

A fault-tolerant logic and implementation method technology, applied in the field of quantum computing and quantum error-correcting codes, can solve the problems of high resource consumption, fault-tolerant logic H gate implementation process, and no consideration of single-qubit, etc., to improve scalability, avoid The effect of repeated measurements

Active Publication Date: 2021-05-18
XIDIAN UNIV
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Problems solved by technology

[0005] The purpose of the present invention is to overcome the defects of the above-mentioned prior art, and proposes a method for implementing a fault-tolerant logic H gate based on RMQC codes, in order to solve the fault-tolerant logic H gate implementation that does not consider single-qubit errors in the prior art The process is fault-tolerant and the technical problem of repeated measurement of the stabilizer leads to large resource consumption

Method used

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  • Implementation method of fault-tolerant logic h-gate based on rmqc code
  • Implementation method of fault-tolerant logic h-gate based on rmqc code
  • Implementation method of fault-tolerant logic h-gate based on rmqc code

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Embodiment 1

[0045] This embodiment is used in the coded state |Ψ> RMQC(4) Fault-tolerant logic H gates are implemented.

[0046] refer to figure 1 , the present invention comprises the following steps:

[0047] Step 1) For the encoded state |Ψ> RMQC(4) Add an H gate for each qubit of :

[0048] pair containing three stable subgroups and The encoded state of |Ψ> RMQC(4) After numbering the 15 qubits in , add the H gate to get the intermediate state where |Ψ> RMQC(4) The number of stabilizers included is 14, which are Contains 4 X stabilizers, 4 Z stabilizers included, and Contains 6 Z stabilizers;

[0049] Step 2) Get three stable subgroups and The symptom value corresponding to each stabilizer in :

[0050] Step 2a) Yes The Z stabilizer in and The X stabilizers in are measured separately to get the symptom value corresponding to each Z stabilizer Symptom value corresponding to each X stabilizer i∈{1,2,...,6}, j∈{1,2,...,4}, get symptom value for:

[0051...

Embodiment 2

[0093] This embodiment is the same as step 1) to step 4) and step 7) to step 8) in embodiment 1, only step 5) and step 6) have been modified, for the coded state |Ψ> RMQC(5) Fault-tolerant logic H gates are implemented.

[0094] refer to figure 1 ,

[0095] Step 5) to All Z stabilizers included are grouped:

[0096] In each x-model contained in the 5-model, the two vertices of the inner model and the outer model respectively belong to Z stabilizer Bilaterally stabilized subgroups x∈{4,5}, index∈{1,2,...,(x-1)×2 5-x}, all x-models correspond to two-sided stable subgroups Combined into a set of bilaterally stable subgroups in:

[0097]

[0098]

[0099] in:

[0100]

[0101]

[0102]

[0103]

[0104] Also divide each x-model contained in the 5-model other than Z stabilizer Combined into one-sided stabilized subgroups All x-models correspond to one-sided stable subgroups Combined into a set of one-sided stable subgroups in:

[0105]...

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Abstract

The invention proposes an implementation method of a fault-tolerant logic H gate based on RMQC codes, which solves the problems of fault tolerance caused by single qubit errors and large resource consumption caused by repeated measurement of stabilizers. The implementation steps are: add H gate to the encoded state to obtain the intermediate state; measure the stabilizer to obtain the symptom value; obtain the type and location of the single qubit error according to the symptom value; establish the graphical model of the RMQC code; Carry out geometric classification; group stabilizers according to their geometric types and determine their corresponding repair operators; correct the symptom value according to the single qubit error, and determine the repair operator for repairing the intermediate state according to the corrected symptom value; The repair operator and single-qubit errors are then added to the intermediate state. The invention has fault tolerance and high resource utilization rate, and can be used to realize the fault-tolerant universal logic gate set in quantum computers.

Description

technical field [0001] The invention belongs to the technical field of quantum computing and quantum error correction codes, and relates to a method for realizing a fault-tolerant logic H gate, in particular to a method for realizing a fault-tolerant logic H gate based on RMQC codes, which can be applied to fault-tolerant general logic gates in quantum computers realization of the set. Background technique [0002] Quantum computing has attracted the attention of people from all walks of life because of its potential powerful computing power. Its essence is to use quantum coherence to complete quantum computing. However, in practical applications, maintaining this state of quantum coherence is very difficult. Therefore, in order to realize quantum computing, a key issue is to overcome the phenomenon of quantum decoherence. Coding qubits is one of the effective ways to solve this problem, so people have invested a lot of energy in quantum error-correcting codes. However, t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/13
Inventor 权东晓牛力朱莉莉朱畅华赵楠易运晖何先灯陈南
Owner XIDIAN UNIV
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