A three-dimensional on-chip routing device based on recalculation and a method thereof

Abstract

The invention provides a three-dimensional on-chip routing device based on recalculation. The three-dimensional on-chip routing device based on recalculation comprises an input port, a bypass cache injection unit, a local discharge unit, an address calculation unit, a priority ranking unit, a bypass cache discharge unit, a recalculation unit and an output port which are sequentially connected through a transmission channel. Wherein the recalculation unit is used for recalculating the priority of the data packet, and when the data packet is about to be transmitted to the next device, the recalculation unit recalculates the priority of the data packet according to a recalculation strategy. On one hand, it is guaranteed that the data packet priority is reasonable; on the other hand, it can beguaranteed that the data packet priority is always effective from data packet sending to data packet receiving, and the situation of wrong steering is avoided. Meanwhile, the method well solves the problem that the local data packet cannot be discharged to the IP core in time and is turned to be transmitted and even forms the bypass transmission, reduces the number of times of turning transmission and bypass transmission of the local data packet, and further reduces the transmission delay of the data packet in the network.

Description

technical field [0001] The invention relates to the field of on-chip networks in integrated circuits, in particular to a recalculation-based three-dimensional on-chip routing device and method thereof. Background technique [0002] With the development of three-dimensional integrated circuits and the continuous expansion of the scale of the network on chip, researchers first proposed a three-dimensional network on chip (Three-Dimensional Network on Chip, 3D NoC) in 2005. 3D NoC shortens the physical connection length, reduces data transmission delay, and improves chip integration density. Under the same network scale, 3D NoC can improve the performance by about 33% compared with the plane-limited 2D NoC, which has attracted widespread attention from academia and industry for its important academic value and broad application development prospects. As the decider of the data packet transmission mode of the 3D on-chip network, the 3D on-chip routing method can not only improv...

AI Technical Summary

Problems solved by technology

[0003] The cache in the three-dimensional on-chip router can be used to store data packets that have failed to compete or are waiting to be transmitted. Therefore, introducing a cache in the on-chip router can resolve packet conflicts in the network and improve bandwidth. However, the introduction of the cache not only increases the design of the on-chip router. Difficulty (packet cache logic and flow control strategy), also consumes a lot of network resources

Once the priority mechanism is invalid, the high-priority data packets that should not be diverted are redirected incorrectly, causing the data packets to be far away from the destination node, increasing the transmission delay and the number of data packet diversions, and reducing the network transmission performance

Currently there are Age-based [1] 、Golden Packet [2] and Silver Flit [3] priority mechanism, but the priority allocation mechanism based on Age will take up a lot of space in the packet header, and it is necessary to add a larger comparator to the arbitration unit of the router, resulting in waste of resources

The priority allocation mechanism based on Golden Packet and Silver Flit cannot guarantee that data packets have the same priority in downstream routers

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