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Method for manufacturing semiconductor structure

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of bottom silicide layer damage, contact plug critical dimension window shrinkage, etc.

Inactive Publication Date: 2019-07-12
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, typical etch-back operations may induce profile kinks in the metal layer, and profile kinks may shrink the CDW of the contact plugs.
On the other hand, heavy etch operations can cause damage to the bottom silicide layer

Method used

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  • Method for manufacturing semiconductor structure
  • Method for manufacturing semiconductor structure
  • Method for manufacturing semiconductor structure

Examples

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Embodiment Construction

[0019] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, such components and arrangements are examples only and are not intended to be limiting. For example, in the following description, forming a first device over or on a second device may include embodiments where the first device and the second device are formed in direct contact, and may also include embodiments where the first device and the second device are formed in direct contact. An embodiment in which an additional device is formed in between so that the first device and the second device may not be in direct contact. Additionally, the present disclosure may repeat figure numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship...

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PUM

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Abstract

A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificialportion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thicknessof the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed, with at least a portion of the first conductive portion remaining over the bottom of the trench.

Description

technical field [0001] The present disclosure relates to a manufacturing method of a semiconductor structure. Background technique [0002] Transistors typically include semiconductor regions for forming source and drain regions. The contact resistance between the metal conductive via and the semiconductor region is high. Therefore, a metal silicide is formed on the surface of a semiconductor region such as a silicon region, a germanium region, or a silicon germanium region to reduce contact resistance. The conductive via is formed in contact with the silicide region, and the contact resistance between the conductive via and the silicide region is low. [0003] A typical silicidation process includes forming a metal layer on the surface of a semiconductor region, and then performing annealing so that the metal layer reacts with the semiconductor region to form a silicide region. After the reaction, the upper portion of the metal layer may remain unreacted. An etch-back o...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/285H01L21/768
CPCH01L21/28518H01L21/76877H01L21/76882H01L29/401H01L29/66545H01L29/785H01L29/456H01L29/41791H01L21/823431H01L21/76843H01L21/76865H01L21/76855H01L21/76846H01L21/76847H01L21/76831
Inventor 廖佑祥李雅惠朱立伟聂君文黄鸿仪张志维苏庆煌
Owner TAIWAN SEMICON MFG CO LTD