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A Wafer Tape-Out Surface Flatness Detection Device That Avoids False Defects

A surface flatness and detection device technology, which is applied in semiconductor/solid-state device testing/measurement, electrical components, circuits, etc., can solve problems such as increasing processing costs, reducing production efficiency, and inaccurate data, so as to avoid secondary maintenance, Reduce processing costs and scan comprehensive results

Active Publication Date: 2021-05-18
SHENZHEN SMARTMORE TECH CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The main purpose of the present invention is to overcome the deficiencies of the prior art and provide a device for detecting the surface flatness of wafer tape-outs that avoids false defects, so as to solve the problem of dust falling or tiny parts falling frequently during wafer processing. On the wafer, the data is inaccurate when the equipment scans the wafer, and the qualified wafer is judged as a defective product, resulting in a secondary inspection of the qualified product, which increases the processing cost and reduces the production efficiency.

Method used

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  • A Wafer Tape-Out Surface Flatness Detection Device That Avoids False Defects
  • A Wafer Tape-Out Surface Flatness Detection Device That Avoids False Defects
  • A Wafer Tape-Out Surface Flatness Detection Device That Avoids False Defects

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Embodiment Construction

[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0027] see Figure 1-9 , the present invention provides a technical scheme of a wafer surface flatness detection device that avoids false defects: its structure includes a test frame 1, a scanning board 2, and a delivery table 3, and the test frame 1 is connected to the scanning board 2 by rails. The scanning board 2 is threadedly connected with a threaded rod 20, the threaded rod 20 is installed on the test frame 1, the scanning board 2 can be lifted, and the...

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Abstract

The invention discloses a device for detecting the surface flatness of wafer tape-outs which avoids false defects. Its structure includes a test frame, a scanning board, and a conveying table. Threaded rod, the threaded rod is installed on the test frame, the test frame is locked with the conveying platform, the conveying platform is composed of a surrounding frame, a lock hole, a locking plate, and an internal device, and the surrounding frame is equipped with a locking hole, Locking plate, the internal device is installed on the surrounding frame. When the wafer of the present invention is flow-processed and passes through the detection device, it is scanned and detected by the scanning board. If it is a qualified product, it will continue to be transported to the next process on the conveyor table. Residual products, the internal device is running, and the internal scanning device is used for secondary scanning detection. The side scanning of the internal scanning device can more accurately determine whether it is a false defect, avoiding secondary inspections on qualified products, and reducing processing costs. , improving production efficiency.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a device for detecting the surface flatness of wafer tape-outs which avoids false defects. Background technique [0002] The detection of the flatness of the wafer surface is for the needs of lithography and for the performance considerations of integrated circuits; tape-out refers to the manufacture of chips through a series of process steps like an assembly line; in the field of integrated circuit design, "flow-out" refers to It is "trial production", that is to say, after the circuit is designed, a few dozens of pieces are produced for testing. If the test passes, mass production will start like this. [0003] In the prior art, when wafers are processed, dust or fine parts often fall on the wafers, resulting in inaccurate data when the equipment scans the wafers, and judges qualified wafers as defective products, resulting in Secondary inspection of qualified products increases ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66H01L21/67
CPCH01L21/67271H01L21/67288H01L22/12H01L22/20
Inventor 周淑英黄梅玉骆伟秋饶榕琦
Owner SHENZHEN SMARTMORE TECH CO LTD
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