Statistical timing analysis method for integrated circuits under advanced technology and low voltage
An advanced technology and integrated circuit technology, applied in CAD circuit design, calculation, electrical digital data processing, etc., can solve problems such as large timing margin, timing violation, and inability to meet design function and performance requirements
Active Publication Date: 2020-11-24
SOUTHEAST UNIV
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Problems solved by technology
Obviously, the scaling factor varies with the cell type, size, load, and process angle in the circuit. Improper setting will either lead to timing violations in the case of integrated circuit delay fluctuations, that is, it cannot meet the predetermined design function and performance requirements, or lead to excessive timing margins. Large, in order to accommodate the extreme conditions of the circuit, the energy efficiency is reduced
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[0052] The technical solution of the present invention will be further introduced below in combination with specific embodiments.
[0053] This specific embodiment discloses an advanced technology and a method for statistical timing analysis of integrated circuits under low voltage. The advanced technology refers to the technology below 40nm, and the low voltage refers to the working voltage of the integrated circuit lower than the transistor threshold voltage of 0.35V. The circuit path of an integrated circuit contains at least two levels of circuit cells; for example: an integrated circuit may be a chain of buffers, such as figure 2 As shown, one of the inverters is used as a first-level circuit unit.
[0054] This method comprises the following steps:
[0055] S1: According to the nominal delay value of the circuit units at all levels in the circuit path under the non-step input signal and the nominal delay value of the circuit unit at the current level under the step inp...
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The invention discloses a statistical timing analysis method for integrated circuits under advanced technology and low voltage. By simulating and modeling the process parameter fluctuations of integrated circuits under advanced technology, based on the relationship between integrated circuit delay and process parameters under low voltage Establish a circuit timing statistical model to analyze the maximum delay and minimum delay in the case of integrated circuit timing fluctuations. Compared with the traditional static timing analysis method, the ability to more accurately analyze the circuit delay distribution under process parameter fluctuations is of great significance for advanced technology and integrated circuit design under low voltage.
Description
technical field [0001] The invention relates to timing analysis of integrated circuits manufactured with advanced technology under low voltage, in particular to a statistical timing analysis method for integrated circuits under advanced technology and low voltage. Background technique [0002] With the continuous growth of the scale and computing power of integrated circuits, energy consumption has gradually become an important limitation restricting the development of various computing systems, including the Internet of Things, embedded devices, mobile terminals, supercomputing and data centers. The development of energy-efficient integrated circuit technology is an important means to solve the problem of energy consumption in computing systems. Traditional integrated circuits meet the requirements of reducing chip energy density by pursuing advanced process size and proportional scaling of power supply voltage. However, with the development of Moore's Law and Dennard Scali...
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IPC IPC(8): G06F30/3312
CPCG06F30/3312G06F30/3315G06F2111/08G06F30/367G06F2119/12
Inventor 曹鹏杨泰郭静静
Owner SOUTHEAST UNIV