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Integrated circuit statistical time sequence analysis method under advanced process and low voltage

An integrated circuit and advanced technology technology, applied in the field of timing analysis of integrated circuits at low voltage, can solve problems such as timing violations, large timing margins, and inability to meet design function and performance requirements

Active Publication Date: 2019-11-12
SOUTHEAST UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Obviously, the scaling factor varies with the cell type, size, load, and process angle in the circuit. Improper setting will either lead to timing violations in the case of integrated circuit delay fluctuations, that is, it cannot meet the predetermined design function and performance requirements, or lead to excessive timing margins. Large, in order to accommodate the extreme conditions of the circuit, the energy efficiency is reduced

Method used

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  • Integrated circuit statistical time sequence analysis method under advanced process and low voltage
  • Integrated circuit statistical time sequence analysis method under advanced process and low voltage
  • Integrated circuit statistical time sequence analysis method under advanced process and low voltage

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Embodiment Construction

[0052] The technical solution of the present invention will be further introduced below in combination with specific embodiments.

[0053] This specific embodiment discloses an advanced technology and a method for statistical timing analysis of integrated circuits under low voltage. The advanced technology refers to the technology below 40nm, and the low voltage refers to the working voltage of the integrated circuit lower than the transistor threshold voltage of 0.35V. The circuit path of an integrated circuit contains at least two levels of circuit cells; for example: an integrated circuit may be a chain of buffers, such as figure 2 As shown, one of the inverters is used as a first-level circuit unit. This method comprises the following steps:

[0054] S1: According to the nominal delay value of the circuit units at all levels in the circuit path under the non-step input signal and the nominal delay value of the circuit unit at the current level under the step input signal...

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Abstract

The invention discloses an integrated circuit statistical time sequence analysis method under advanced process and low voltage. Simulation modeling is performed on the process parameter fluctuation condition of an integrated circuit under the advanced process, a circuit time sequence statistical model is established based on the relationship between the integrated circuit time delay and the process parameters under the low voltage, and the maximum time delay and the minimum time delay under the integrated circuit time sequence fluctuation condition are analyzed. Compared with a traditional static timing sequence analysis method, the method has the advantages that the circuit delay distribution condition under process parameter fluctuation can be analyzed more accurately, and the method isof great significance to integrated circuit design under advanced processes and low voltage.

Description

technical field [0001] The invention relates to timing analysis of integrated circuits manufactured with advanced technology under low voltage, in particular to a statistical timing analysis method for integrated circuits under advanced technology and low voltage. Background technique [0002] With the continuous growth of the scale and computing power of integrated circuits, energy consumption has gradually become an important limitation restricting the development of various computing systems, including the Internet of Things, embedded devices, mobile terminals, supercomputing and data centers. The development of energy-efficient integrated circuit technology is an important means to solve the problem of energy consumption in computing systems. Traditional integrated circuits meet the requirements of reducing chip energy density by pursuing advanced process size and proportional scaling of power supply voltage. However, with the development of Moore's Law and Dennard Scali...

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/3312G06F30/3315G06F2111/08G06F30/367G06F2119/12
Inventor 曹鹏杨泰郭静静
Owner SOUTHEAST UNIV