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CRC parallel encoding and decoding method and encoder/decoder based on CRC parallel encoding and decoding method

A technology of encoding method and decoding method, which is applied in the field of CRC parallel encoding and decoding methods and codecs based on it, can solve problems such as long delay, achieve fast encoding and decoding, and achieve the effect of encoding and decoding

Active Publication Date: 2019-11-26
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology

However, the serial code of CRC is a single-bit input, the implementation structure is simple, and the delay is relatively long, so it is only suitable for low-speed serial communication

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  • CRC parallel encoding and decoding method and encoder/decoder based on CRC parallel encoding and decoding method
  • CRC parallel encoding and decoding method and encoder/decoder based on CRC parallel encoding and decoding method
  • CRC parallel encoding and decoding method and encoder/decoder based on CRC parallel encoding and decoding method

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Embodiment Construction

[0056] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0057] The present invention provides a fast CRC parallel encoding and decoding method. The method includes: according to the generating polynomial of CRC, using formula recursive method, matrix operation is performed on parallel input data that needs to be encoded / decoded, and the matrix operation is performed by an exclusive OR circuit. Realization: By complementing the delay of each data path, the smallest delay time difference is obtained, and then the maximum time difference pipeline technology is used to realize fast encoding and decoding operations.

[0058] Through the foregoing implementation method, the first embodiment of the present invention provides an encoder, including:

[0059] The register unit includes a ...

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Abstract

The invention discloses a CRC parallel encoding and decoding method and an encoder / decoder based on the CRC parallel encoding and decoding method. The method mainly comprises the steps: sequentially inputting to-be-encoded / decoded data into the encoder / decoder, wherein the to-be-encoded / decoded data are inputted into the encoder / decoder in a parallel input mode; in the encoder / decoder, enabling the encoding / decoding data to be combined with a generator polynomial of a CRC to perform matrix operation to obtain an encoding / decoding result of the encoding / decoding data. According to the CRC parallel encoding and decoding method and the encoder / decoder based on the CRC parallel encoding and decoding method, a formula recursion method is used for operating parallel input data of each clock, andrapid encoding and decoding are realized by applying a maximum time difference pipeline technology; matrix operation is achieved through an exclusive-OR circuit, delay of each data path is supplemented, the minimum delay time difference is obtained, and rapid encoding and decoding operation is achieved through the assembly line technology.

Description

Technical field [0001] The present invention relates to the field of communications, in particular to a CRC parallel coding and decoding method and a codec based on the same. Background technique [0002] In a digital communication system, in order to improve the reliability of channel transmission and to be able to judge the correctness of the data at the receiving end, in addition to channel coding technology, verification technology is usually used. Cyclic Redundancy Check (CRC), with its strong error detection ability and excellent anti-interference performance, has been widely used in many communication systems, such as: Ethernet, satellite communications, etc. It also plays a very important role in the codec system. [0003] The realization of CRC is to use the principle of linear code to generate an r-bit check code for the encoded k-bit binary data according to certain rules, which is appended to the original data to form a (k+r)-bit binary data. Send it out together. At...

Claims

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Application Information

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IPC IPC(8): H03M13/09
CPCH03M13/091
Inventor 陈容陈岚张义恒
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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