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Semiconductor devices capable of holding height of alignment markers

By using silicon oxycarbide capping structure and filling structure during the manufacturing process of semiconductor devices, the problem of alignment mark height variation during the polishing process is solved, ensuring the maintenance of alignment marks and normal manufacturing of semiconductor devices.

Active Publication Date: 2020-01-24
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, for example, in a polishing process performed after patterning the insulating layer, most of the alignment marks may be removed and their original heights cannot be maintained.
Therefore, the alignment marks may not work properly due to their altered height

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0013] Hereinafter, semiconductor devices according to embodiments of the present disclosure will be described more fully with reference to the accompanying drawings.

[0014] Figure 1 to Figure 20 are plan views and cross-sectional views showing some stages in a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. specifically, figure 1 , Figure 4 , Figure 7 , Figure 10 with Figure 13 is a planar graph, and Figure 2 to Figure 3 , Figure 5 to Figure 6 , Figure 8 to Figure 9 , Figure 11 to Figure 12 with Figure 14 to Figure 20 is a cross-sectional view.

[0015] figure 2 , Figure 8 , Figure 11 with Figure 14 are the cross-sectional views taken along the line A-A' of the corresponding plan, respectively, image 3 , Figure 5 , Figure 9 , Figure 12 with Figure 15 to Figure 20 are the cross-sectional views taken along the line B-B' of the corresponding plan view, respectively, and Image 6 is a cr...

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PUM

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Abstract

A semiconductor device may include a gate electrode structure on a first region of a substrate including the first region and a second region, a capping structure covering an upper surface of the gateelectrode structure, the capping structure including a capping pattern and a first etch stop pattern covering a lower surface and a sidewall of the capping pattern, an alignment key on the second region of the substrate, the alignment key including an insulating material, and a filling structure on the second region of the substrate, the filling structure covering a sidewall of the alignment key,and including a first filling pattern, a second filling pattern covering a lower surface and a sidewall of the first filling pattern and a second etch stop pattern covering a lower surface and a sidewall of the second filling pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS [0002] This application claims the benefit of Korean Patent Application No. 10-2018-0083152 filed on Jul. 17, 2018 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field [0003] Embodiments of the present disclosure relate to a semiconductor device. More specifically, embodiments of the present disclosure relate to a semiconductor device including a capping layer, which may cover an upper surface of a conductive pattern. Background Art [0004] When forming an alignment mark by patterning an insulating layer during the manufacture of a semiconductor device, the height of the alignment mark should be maintained throughout the manufacturing process. However, in a polishing process performed after patterning the insulating layer, for example, a large portion of the alignment mark may be removed and its original height may not be maintained. Therefore, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/544H01L27/088H01L21/8234
CPCH01L23/544H01L2223/54426H10D84/0158H10D84/038H10D84/834H10D30/6219H10D30/62H01L21/76877H01L21/02126H01L21/76816H01L21/76829H10D84/0147H10D84/0149H10D64/68H10D64/514
Owner SAMSUNG ELECTRONICS CO LTD