Parallel Access to Volatile Memory by Processing Device for Machine Learning

A processing device, technology of machine learning, applied in the field of memory system

Pending Publication Date: 2020-03-17
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, the off-chip memory interface suffers from the burden of

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  • Parallel Access to Volatile Memory by Processing Device for Machine Learning
  • Parallel Access to Volatile Memory by Processing Device for Machine Learning
  • Parallel Access to Volatile Memory by Processing Device for Machine Learning

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Embodiment Construction

[0017] At least some aspects of the present disclosure relate to parallel access to volatile memory by a processing device that supports processing of machine learning (eg, neural networks).

[0018] Deep learning machines, such as those that support the processing of Convolutional Neural Networks (CNNs), process to determine an extremely large number of operations per second. For example, input / output data, deep learning network training parameters, and intermediate results are continuously fetched from and stored in one or more memory devices (eg, DRAM). DRAM-type memories are typically used due to their cost advantages when large storage densities are involved (eg, storage densities greater than 100MB). In one example of a deep learning hardware system, a computing unit (eg, a system on a chip (SOC), FPGA, CPU, or GPU) is attached to a memory device (eg, a DRAM device).

[0019] It has been recognized that existing machine learning architectures (eg, as used in deep learni...

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Abstract

The invention relates to parallel access to volatile memory by processing a device for machine learning. A memory system has a processing device (e.g., CPU) and memory regions (e.g., in a DRAM device)on the same chip or die. The memory regions store data used by the processing device during machine learning processing (e.g., using a neural network). One or more controllers are coupled to the memory regions and configured to: read data from a first memory region (e.g., a first bank), including reading first data from the first memory region, where the first data is for use by the processing device in processing associated with machine learning; and write data to a second memory region (e.g., a second bank), including writing second data to the second memory region. The reading of the firstdata and writing of the second data are performed in parallel.

Description

[0001] Related applications [0002] This application claims a US patent application filed on September 11, 2018 and entitled "Parallel Access to Volatile Memory by A Processing Device for Machine Learning" The benefit of the filing date of Serial No. 16 / 127,850, the entire contents of which are incorporated herein by reference as if fully set forth. technical field [0003] At least some embodiments disclosed herein relate generally to memory systems, and more particularly, to parallel access by processing devices to volatile memory for machine learning processing. Background technique [0004] Limited memory bandwidth is a significant problem in machine learning systems. For example, DRAM devices used in current systems store a large number of weights and activations used in deep neural networks (DNNs). [0005] Existing computer architectures use processor chips dedicated to serial processing and DRAM optimized for high-density memory. The interface between these two ...

Claims

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Application Information

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IPC IPC(8): G06F13/16G06F12/06G06F3/06
CPCG06F13/1673G06F12/0646G06F3/0644G06F3/0656G06F3/0683G11C11/54G11C8/12G11C7/1006G06N3/063G06N3/084G06N3/045G11C7/10G06N3/08G06N20/00G06N3/02G06N3/04G11C7/22
Inventor G·戈洛夫
Owner MICRON TECH INC
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