Self-adaptive read path delay calculation method and circuit for DRAM physical interface

A physical interface and path delay technology, which is applied in the adaptive read path delay calculation method and circuit field, can solve the problems of no read data delay calculation, etc., and achieve the effect of accurately calculating the read path delay, simplifying parameter information, and simplifying the method

Active Publication Date: 2020-04-17
XI AN UNIIC SEMICON CO LTD
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Problems solved by technology

[0026] However, this method has limitations. For other DRAMs with different standard interfaces (for example: DDR2 / DDR / SDR DRAM), the MPR function is not available. Therefore, for the application of this type of DRAM, there is no similar Method to perform read data latency calculation
Therefore, when the DRAM chip without the MPR function is working, there are still limitations on how to accurately calculate the return time of the read data

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  • Self-adaptive read path delay calculation method and circuit for DRAM physical interface
  • Self-adaptive read path delay calculation method and circuit for DRAM physical interface
  • Self-adaptive read path delay calculation method and circuit for DRAM physical interface

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[0071] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

[0072] The present invention as figure 1 and figure 2 As shown, considering the impact of various delays in the entire read process on signal transmission, for the physical interface of the memory, whether the correct sampling and transmission of data determines whether the read operation process can be completed correctly. Correctly calculate and judge the arrival time of the read data, and sample and obtain it in time. Its essence lies in the calculation and determination of the signal path delay (the time difference between the time when t...

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Abstract

The invention discloses a self-adaptive read path delay calculation method and circuit for a DRAM physical interface. The method comprises the following steps: inputting a read operation to a physicalinterface of a memory at a fixed moment, then monitoring a physical interface of the memory and a data port on one side of the dynamic random access memory, waiting until a corresponding signal fluctuation moment is found, and locking a time difference. Read data delay calculation can be realized, and read path delay calculation is simplified.

Description

technical field [0001] The invention relates to the field of memory testing, in particular to an adaptive read path delay calculation method and circuit for a DRAM physical interface. Background technique [0002] As a standard physical interface layer, the memory physical interface (Memory PHY or PHY) plays an important role as a bridge between the memory controller (MC Memory Control) and the dynamic random access memory (DRAM), ensuring that the memory and the controller ( Memory controller) Reliability and feasibility of two-way transmission of control signals and read / write data signals and clock signals: [0003] The following is an introduction to the transmission direction of data or commands: [0004] 1. Memory Controller (MC)→Dynamic Random Access Memory (DRAM): [0005] That is, the memory controller sends signals such as commands to the DRAM. [0006] The memory controller obtains the operation information and address of the SOC System On Chip system for the D...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/4076G11C11/409G06F5/08
CPCG11C11/4076G11C11/409G06F5/08
Inventor 王小光
Owner XI AN UNIIC SEMICON CO LTD
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