A configurable parallel bit block interleaver and interleaving method

A packet interleaving and interleaver technology, applied in the field of communication, can solve the problems of high implementation complexity, incompatibility of packet interleavers with various interleaving modes, and high device cost, so as to reduce implementation complexity, reduce read and write address calculation and read Write enable control logic, reduce the effect of operating frequency requirements

Active Publication Date: 2022-07-12
NAT SPACE SCI CENT CAS
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Problems solved by technology

[0006] The purpose of the present invention is to overcome the problems of high hardware implementation complexity, high device cost, and incompatibility of various interleaving modes of the existing serial packet interleaver, thereby providing a configurable parallel bit packet interleaver

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  • A configurable parallel bit block interleaver and interleaving method
  • A configurable parallel bit block interleaver and interleaving method
  • A configurable parallel bit block interleaver and interleaving method

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[0026] The technical solutions of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] In the DVB-S2 standard, it supports 28 kinds of coding and modulation methods, adopts BCH code and LDPC code concatenated error correction coding scheme, supports 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, 8 / 9, 9 / 10, a total of 11 code rates; the available modulation methods include: QPSK, 8PSK, 16APSK, 32APSK. Table 1 lists the coding and modulation modes supported by this standard. The DVB-S2 standard supports two coded data frame (FECFREAM) lengths, which are 16200 and 64800 respectively, and both support these 28 coding and modulation modes.

[0028] Table 1: DVB-S2 standard code modulation method

[0029]

[0030] In the DVB-S2 standard, bit interleaving is required for 8PSK, 16APSK and 32APSK modulation modes, and data is written into the interleaver in the column direction and read horizontally. The interleaving depth a...

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Abstract

A configurable parallel bit packet interleaver and an interleaving method, the interleaver includes a control module and a FIFO storage module; the control module is configured to dynamically reconstruct the FIFO storage module according to input parameters, including the interleaving depth and the interleaving width; and Used to generate a read-write enable signal of the FIFO, and control the read-write operation of the FIFO storage module; the FIFO storage module is used to write the data to be interleaved in parallel by column under the control of the read-write enable signal, and by row Read in parallel to complete parallel bit group interleaving. The interleaver of the present invention has configurability. According to the settings of different VCMs, the interleaving depth and interleaving width of the interleaver are dynamically configured, which can be compatible with different interleaving modes, thereby improving the flexibility and versatility of the interleaver; the interleaver is a parallel interleaver. The bit interleaver improves the data processing speed, shortens the processing delay, and reduces the complexity of implementation.

Description

technical field [0001] The present invention relates to the field of communication technologies, in particular to a configurable parallel bit grouping interleaver and an interleaving method. Background technique [0002] In a digital communication system, due to various interferences in the transmission process, some random errors and burst errors will appear in the final received signal, and errors often occur in clusters. However, channel coding can only detect and correct a single error and Not too long mistakes. Using interleaving technology, the order of bits can be scrambled, so that successive bits in a frame of data are sent in a non-sequential manner, eliminating the correlation between adjacent bits and breaking up long burst errors. Under the premise of not increasing the coding overhead, the error correction performance and reliability of the system are improved. [0003] According to different interleaving methods, interleaving techniques are divided into pack...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L1/00
CPCH04L1/0071H04L1/0061H04L1/0064
Inventor 康婧安军社王冰冰
Owner NAT SPACE SCI CENT CAS
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