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Semiconductor package

A semiconductor and packaging technology, applied in the field of semiconductor packaging

Pending Publication Date: 2020-04-21
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] An aspect of the present disclosure can provide a semiconductor package that can solve problems due to mounting of surface mount components

Method used

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  • Semiconductor package
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Examples

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Embodiment Construction

[0027] Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the accompanying drawings. In the drawings, the shapes, sizes, etc. of components may be exaggerated or reduced for clarity.

[0028] Here, for the sake of convenience, the lower side, lower part, lower surface, etc. are used to indicate the downward direction in relation to the cross-section of the drawing, and the upper side, upper part, upper surface, etc. are used to indicate the opposite direction to the downward direction. . However, these directions are defined for convenience of explanation, and the claims are not particularly limited by the directions defined above, and the concepts of upper and lower are interchangeable with each other.

[0029] In the specification, the meaning of "connection" of a component to another component conceptually includes indirect connection through an adhesive layer between two components as well as direct connection between two comp...

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Abstract

A semiconductor package includes: a connection structure having first and second surfaces opposing each other and including a redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; a passivation layer disposed on the second surface of the connection structure and having a plurality of first and second openings exposing, respectively, first and second regions of the redistribution layer; and a plurality of underbump metal bumps connected to the first region of the redistribution layer through the plurality of first openings, respectively.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2018-0122060 filed on October 12, 2018 at the Korean Intellectual Property Office, the entire disclosure of which is hereby incorporated by reference. technical field [0002] The present disclosure relates to a semiconductor package. Background technique [0003] A significant recent trend in the development of technologies related to semiconductor chips has been the reduction in size of semiconductor chips. Therefore, in the field of package technology, according to the rapid increase in demand for small-sized semiconductor chips and the like, it has been required to realize a semiconductor package having a compact size while including a plurality of pins. One package technology proposed to meet the technical needs described above may be a fan-out package. Such a fan-out type package has a compact size and may allow a plurality of pins to be realized by redistributing connection t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/498
CPCH01L23/49838H01L23/49816H01L23/5389H01L23/13H01L23/49827H01L24/20H01L2224/12105H01L2224/04105H01L24/19H01L2225/1035H01L2225/1041H01L2225/1058H01L2924/3025H01L23/562H01L23/3128H01L21/568H01L25/16H01L23/528H01L23/525H01L24/06H01L24/14H01L23/31H01L21/563H01L23/04H01L2221/68359H01L23/3135H01L23/49822H01L21/4857H01L21/6836H01L21/4853H01L2924/19102H01L2221/68345
Inventor 金正守韩平和裴成桓李镇洹
Owner SAMSUNG ELECTRONICS CO LTD