CPU reset control method and system and storage medium

Abstract

The invention discloses a CPU reset control method and system and a storage medium, and the method comprises the steps: enabling a CPLD to transmit an external interruption signal to a CPU before a monitoring chip or the CPLD logic resets the CPU; enabling the CPU to respond to the external interrupt signal, and closing all DDR2 modules to be accessed by the CPU, a DDR2 controller and a clock signal sent to the DDR2 in an interrupt service program; enabling the CPU to execute writing of a CPLD register according to part of the instructions locked in the instruction cache and confirms resetting; and enabling the CPLD to pull down the hardware reset pin of the CPU, truly resetting the CPU, and if the monitoring chip is reset, pulling down the hardware reset pin of the CPU after time delay,and truly resetting the CPU. According to the method, before the CPLD needs to reset the CPU, all accesses to the DDR2 memory are closed by the CPU, and after the CPLD delays for one second and the interior of the DDR2 is not accessed, the CPU is reset.

Description

technical field [0001] The invention relates to the technical field of computer embedded drive, in particular to a CPU reset control method, system and storage medium. Background technique [0002] Embedded environments, like ordinary desktop systems, often restart the entire system. Windows and linux desktop systems generally reset the system by manually clicking or commanding. When resetting, various resources will be closed to save files, etc., to prevent file damage or even disk damage. When the embedded system needs to be reset, it may be directly controlled by the monitoring chip (commonly known as watchdog, watchdog, which is essentially a timer circuit, generally has an input and an output, and the input is called feeding the dog. The output is generally connected to the reset terminal of another part, usually connected to the single-chip microcomputer; the function of the watchdog is to check the internal situation of the chip regularly, and once an error occurs, i...

AI Technical Summary

Problems solved by technology

If it is reset by the watchdog, it may not be possible to implement these operations at all

[0003] At the same time, the early DDR2 (DDR=Double Data Rate, double rate, DDR SDRAM=double rate synchronous dynamic random access memory, people used to call it DDR, which is usually called running memory, DDR2 is the second generation DDR) memory, is not With hardware reset function, if the reset is forced, the internal state of the DDR2 chip may be wrong, the memory reads and writes are inconsistent, the CPU cannot execute instructions correctly, and the embedded system can no longer be started unless the power is turned off and restarted

In general hardware design, it is not good to power on and off DDR2 separately. Once the embedded system cannot be restarted normally, the device will be paralyzed in an unattended environment. Unless manual intervention, the consequences are very serious.

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