Image processor

Abstract

An image processing device having a plurality of cores which attains more efficient memory access than conventionally attained. In the image processing device employing pipeline processing, a memory access section 20 executes data transfer between an operation section 10 including a plurality of cores each performing operation for image processing and an external memory 2. The memory access section 20 has an access schedule storage portion 22 which stores types of data transfers per stage, and executes data transfer between the operation section 10 and the external memory 2 in accordance with the storage contents of the access schedule storage portion 22. A system control section 30 sets the types of data transfers in the access schedule storage portion 22 at a stage preceding the stage at which the data transfers are executed. This makes it possible to change the types of data transfers with stages flexibly and thus allows the memory access section 20 to execute only necessary data transfers at each stage without the necessity of arbitration.

Description

technical field [0001] The invention relates to an image processing device, in particular to a technology for controlling access requirements of multiple cores to memory. Background technique [0002] In the following, MPEG2 video coding is taken as an example to describe the prior art. [0003] In MPEG2 video coding, the entire image is divided into macroblocks with a unit of 16 pixels in length and 16 pixels in width, and each macroblock forms a grid, so that the image signal is encoded for each macroblock. The encoding process of each macroblock is independent of each other. [0004] In such image coding, pipeline processing is performed in units of macroblocks in order to improve coding efficiency. In order to perform this pipeline processing, the MPEG2 video encoding system is equipped with a plurality of dedicated arithmetic units, which respectively perform arithmetic necessary for encoding such as motion vector detection, DCT (discrete cosine transform) arithmetic,...

AI Technical Summary

Problems solved by technology

[0012] However, if the number of memory access cycles is reduced by setting the cache memory in this way, the power consumption and area of ​​the entire system will increase the portion of the cache memory.

In particular, in the case where the system is implemented as an LSI, an increase in power consumption or area is a serious problem

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