A Layer Assignment Method Considering Bus and Non-Bus Nets

Abstract

The invention relates to the construction of a VLSI mid-level allocator in the technical field of integrated circuit computer aided design. Due to the continuous development of the manufacturing industry and the emergence of the concept of system-on-chip design, the number of buses between modules on a chip has increased rapidly and has become a decisive factor in performance and power consumption. Therefore, the present invention fully considers the important influence of bus on chip design, and proposes a layer allocator considering bus and non-bus nets. The allocator is based on the following three effective methods: 1) a network priority determination method based on a multi-element cost function; 2) a layer adjustment strategy based on a lookup table, which includes a layer adjustment with a limited number of layers technology and a layer adjustment technology with unlimited layers; 3) a bus maximum timing optimization algorithm. The invention can not only ensure less number of through holes, but also can effectively optimize the bus line length deviation, so as to obtain a high-quality layer allocation result.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit computer-aided design, and in particular relates to a layer allocation method considering bus and non-bus network. Background technique [0002] In the current VLSI design, with the development of process technology, the timing problems in the circuit are becoming more and more prominent, which increasingly affects the performance and output of the new generation of chips. At the same time, with the emergence of the concept of system-on-chip, the wide application of intellectual property modules has become the mainstream of chip design, which makes the number of buses between different modules on the chip increase rapidly. Especially in the multi-core system-on-chip design, the bus has become the decisive factor for performance and power consumption. For a bus, it carries multiple signals and consists of a source pin group and one or more sink pin groups. If the line lengths of each s...

AI Technical Summary

Problems solved by technology

The existing layer allocator does not consider the timing matching problem of the bus, which leads to the deterioration of the timing, which is far from the actual chip development trend

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