Layer allocation method considering bus and non-bus networks

Abstract

The invention relates to construction of a middle-layer distributor of a super-large-scale integrated circuit in the technical field of integrated circuit computer aided design. Due to continuous development of the manufacturing industry and appearance of a system-on-chip design concept, the number of buses between modules on a chip is rapidly increased and becomes a decisive factor of performanceand power consumption. Therefore, the important influence of the bus on the chip design is fully considered, and the layer distributor considering the bus and non-bus networks is provided. The distributor is based on the following three effective methods: 1) a wire network priority determination method based on a multi-element cost function; 2) a layer adjustment strategy based on a lookup table,wherein the layer adjustment strategy comprises a layer number limited layer adjustment technology and a layer number unlimited layer adjustment technology; 3) a bus maximum time series optimizationalgorithm. It can be guaranteed that the number of generated through holes is small, the bus length deviation can be effectively optimized, and therefore a high-quality layer distribution result is obtained.

Description

technical field [0001] The invention belongs to the technical field of computer-aided design of integrated circuits, and in particular relates to a layer allocation method considering bus lines and non-bus lines. Background technique [0002] In the current VLSI design, with the development of process technology, the timing problem in the circuit is becoming more and more prominent, which will increasingly affect the performance and yield of the new generation of chips. At the same time, with the emergence of the concept of system-level chips, the wide application of intellectual property modules has become the mainstream of chip design, which makes the number of buses between different modules on the chip also increase rapidly. Especially in multi-core SoC design, the bus has become the decisive factor of performance and power consumption. For a bus, it carries multiple signals and consists of a source pin group and one or more sink pin groups. If the line lengths of the ...

AI Technical Summary

Problems solved by technology

The existing layer allocator does not consider the timing matching problem of the bus, which leads to the deterioration of the timing, which is far from the actual chip development trend

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