Automatic layout wiring generation method based on sparse grids

A sparse grid, grid line technology, applied in special data processing applications, instruments, electrical digital data processing and other directions, can solve problems such as the efficiency cannot be optimized, the recording space is large, and the Hightower algorithm cannot be searched, etc. The effect of increasing space and exploring space, decreasing space availability, and decreasing storage space

Active Publication Date: 2020-07-03
SEMITRONIX
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AI Technical Summary

Problems solved by technology

However, the efficiency of the two algorithms cannot reach the optimal
[0005]3. Line exploration method: Searching for wiring methods through line exploration can greatly save the space consumption of algorithm exploration, but the Hightower algorithm may not be able to search for the original existence route; Mikami algorithm cannot guarantee the shorte

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  • Automatic layout wiring generation method based on sparse grids
  • Automatic layout wiring generation method based on sparse grids
  • Automatic layout wiring generation method based on sparse grids

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Embodiment Construction

[0059] Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

[0060] Such as figure 1 An automatic layout and routing generation method for sparsely divided grids is shown, which specifically includes the following steps:

[0061] Step (1), initialize settings:

[0062] Set the winding width to m, the winding gap to n, get all the components to be routed, and mark the pins of the components to be routed as unused.

[0063] Step (2), obtain wiring information:

[0064] Select two components to be routed, determine the route area, and obtain all obstacles that cannot be routed in the route area, including the existing route topology in the route area.

[0065] Select one pin from the unused pins of the two components as the start pin and the destination pin respectively. The method of determining the starting pin and the destination pin is as follows: for the two selected components to be routed, set one...

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Abstract

The invention relates to an automatic layout wiring generation method based on sparse grids. The method comprises the following steps: 1, initialization setting; 2, acquiring wiring information; 3, dividing grids; 4, marking a grid state; 5, wiring; and 6, inquiring whether components to be wired exist or not, and if yes, repeating the step (2) until wiring of all layouts is completed. According to the invention, design requirements can be met according to different devices and layouts; according to the method and the system, the wiring grids are adaptively and reasonably divided to obtain thedata of the related grids, and then the grids are explored by adopting the algorithm, so that the defect of large storage space caused by uniform grid division can be greatly reduced, the space effectiveness is favorably reduced, and the space use efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an automatic layout and wiring generation method based on sparse grids. Background technique [0002] With the rapid development of integrated circuit technology, integrated circuits have entered the era of ultra-deep submicron, which makes the feature size of electronic devices smaller and smaller, the scale of chips is larger and larger, and more and more components can be integrated in a single On the chip, the complexity has risen sharply, and for the wiring method in the layout, the manual design wiring method has long been unable to meet the needs of integrated circuit design, and computer automatic wiring has occupied an increasing proportion of layout design and wiring. The wiring algorithm has an extremely important impact on the speed and efficiency of wiring. How to design an algorithm that requires less time and space, lower complexity, and higher efficien...

Claims

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Application Information

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IPC IPC(8): G06F30/392G06F30/394
Inventor 邵康鹏杨慎知陆梅君
Owner SEMITRONIX
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