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Array data bit inversion

A digital line, charge transfer technology, used in digital memory information, information storage, static memory and other directions

Active Publication Date: 2020-07-07
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to this offset, ferroelectric memory cells can experience performance degradation during subsequent write or read operations

Method used

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  • Array data bit inversion
  • Array data bit inversion
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Examples

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Embodiment Construction

[0023] A memory cell, such as a ferroelectric memory cell, can be written with charge associated with one logic state (the intended logic state), and then the cell can be rewritten with charge associated with a different inverted logic state. This logic state inversion (or bit inversion) can be attributed to storing the same logic state for an extended period of time against the effect on the cell; and despite storing the inverted logic state, the cell can still be read to have the expected logic state. In other words, the charge stored in the cell can be changed in order to mitigate shifting the ferroelectric domain, with the understanding that the logic state stored in the cell can remain unchanged.

[0024] For example, a cell that has stored a charge associated with an intended logic state (eg, a logic 1) for a period of time may be rewritten to store a different charge associated with an inverted logic state (eg, a logic 0). And a subsequent read operation performed on th...

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Abstract

The application relates to array data bit inversion. Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may bethe inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intendedlogic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logicstate inverted from the currently stored logic state.

Description

[0001] Information about divisional applications [0002] This case is a divisional application. The parent case of this divisional case is an invention patent application with an application date of June 1, 2017, an application number of 201780038714.3, and an invention title of "array data bit inversion". [0003] Cross References to Related Applications [0004] This patent application claims priority to PCT Application No. PCT / US2017 / 035452, filed June 1, 2017, entitled "Array DataBit Inversion", which claims June 2016 Priority of U.S. Patent Application No. 15 / 188,890, filed on the 21st, by Ingalls et al., entitled "Array Data Bit Inversion," assigned to its assignee persons, and the entire contents of each of said cases are expressly incorporated herein by reference. technical field [0005] The technical field relates to array data bit inversion. Background technique [0006] The following relates generally to memory devices and more specifically to the perform...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/22G11C7/10
CPCG11C11/2275G11C11/221G11C11/2273G11C7/1006
Inventor C·L·英戈尔斯S·J·德尔纳
Owner MICRON TECH INC