Redundancy error correction structure of OTP

Abstract

The invention discloses a redundancy error correction structure of an OTP. The redundancy error correction structure comprises a redundancy storage array, an address decoding module and a logic control module. The redundant storage array is divided into a space A for storing addresses of damaged storage units and a space B for replacing the damaged storage units; the address decoding module is used for decoding an input address A (8: 0); and the logic control module is used for comparing the input address with the address of the damaged storage unit stored in the space A, and generating a control signal to control the memory reading operation under the condition that the damaged storage unit occurs in the main storage array. According to the redundancy error correction structure, due to the fact that the error rate of the storage array is low and the redundancy storage space is increased in a targeted mode, waste of the chip area is greatly reduced; damaged storage units are directly replaced, logic judgment is not needed, and errors of all storage data types can be corrected; redundancy error correction is achieved through a register, the error correction speed is high, and efficiency is high.

Description

technical field [0001] The invention relates to the application technical field of memory OTP, in particular to an OTP redundant error correction structure. Background technique [0002] At the heart of memory is the storage array. After the chip is taped out, the storage units in some memories will be physically damaged. Physically damaged storage units cannot store and read normal data. The damage of the memory unit reduces the yield of the memory and increases the production cost. In order to overcome the possible physical damage of the storage array in the memory, structures such as redundant storage and redundant replacement are proposed. Redundant storage uses two or more storage units to store the same data. When reading data, read out the data of these memory cells at the same time, and then make a logical decision on the read out data to obtain the final output data. Such a structure wastes more than double the area of ​​the storage space, and the judgment cond...

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Problems solved by technology

[0003] The purpose of the present invention is to provide a redundant error correction structure of OTP, to solve the problem that the existing storage array structure proposed in the above background technology wastes more than double the area of ​​storage space, and the judgment condition can only correct the storage of "0 " or "1" storage unit, the two kinds of errors cannot be corrected at the same time, which reduces the problem of error correction rate

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