Memory control device

Abstract

A memory control apparatus includes one or more memory control logics, one or more memory buses, one or more bus mirroring modules, and one or more bus configuration modules. And the bus mirror imagemodule can change the bus signal connection relationship according to the bus configuration signal and the bus chip selection signal. Therefore, different signals, corresponding to different chip selection signals and having the same or similar pin positions, of the memories on the front and back surfaces of the PCB (printed circuit board) can share the same PCB wire. This helps to simplify the design of the PCB of the storage device and improve signal integrity and bus timing (timing).

Description

technical field [0001] The invention relates to the field of circuit and PCB design, in particular to a memory control device. Background technique [0002] In storage devices based on memory chips such as NAND Flash (flash memory), DRAM, PCM, RRAM, etc., usually a bus in the memory control device can be connected to multiple memory chips, and through chip select signals (such as CE_n or CS) signals to Select to access one of the memory chips. [0003] figure 1 It is a connection schematic diagram of a NAND Flash bus. A memory control device 101 is connected to two pieces of NAND Flash through a NAND Flash bus 102 . The bus signals include: data signal (DQ[7:0]), strobe signal (DQS, DQS_c), control signals such as CLE, ALE, WE_n, RE_n and RE_n_c, and chip select signal 103 . The two NAND Flashes are strobed through chip select signals CE_n[0] and CE_n[1] respectively. When CE_n[0] is low level and CE_n[1] is high level, NAND Flash 0110 is selected; when CE_n[0] is high ...

AI Technical Summary

Problems solved by technology

The cross-connection of a large number of signal lines and the increase in the number of through holes will cause certain difficulties in PCB routing, resulting in an increase in the number of layers, thickness and manufacturing cost of the PCB

Usually this also results in longer trace stubs on the front and back sides

For high-speed buses such as NAND Flash NVDDR3-1200 or SDRAM DDR4-3200, this will adversely affect signal integrity

Moreover, usually the signal trace lengths of the memory on the front and back sides of the PCB will also have a large difference, which is also unfavorable to the bus timing.

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