Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Deep silicon cavity etching method of micro-system module

A microsystem and deep etching technology, applied in the direction of microstructure technology, microstructure devices, manufacturing microstructure devices, etc., can solve the problems of different cavities, difficulty in adjusting the optimal etching passivation ratio, and increased production costs, and achieve Low cost, the effect of solving the problem of large cavity etching

Pending Publication Date: 2020-09-18
浙江集迈科微电子有限公司
View PDF13 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The first wafer-level bonding method can better solve the problem of silicon needles and silicon grass, but the production cost is greatly increased due to the addition of wafer-level bonding steps, and it is difficult to use wafer-level bonding. Realize making cavities with different depths on the same adapter plate
The second method of adjusting the ratio of etching and passivation has higher requirements on etching equipment, the optimal ratio of etching and passivation is difficult to adjust, and the improvement effect is not obvious

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Deep silicon cavity etching method of micro-system module
  • Deep silicon cavity etching method of micro-system module
  • Deep silicon cavity etching method of micro-system module

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0046] like Figure 1 to Figure 9 As shown, a method for etching a deep silicon cavity of a microsystem module specifically includes the following steps:

[0047] 101) Preliminary etching step: coating a photoresist 101 on the upper surface of the wafer, the thickness of the photoresist 101 ranging from 8 microns to 15 microns. Distribute and form at least two or more preliminary cavities on the photoresist 101 through exposure and development technology, the opening size of the preliminary cavities is between 20 microns and 50 microns, and the etching depth is increased, and the etching depth is 20 microns to 80 microns After the etching is completed, the photoresist 101 is removed to form a corresponding small cavity 102 . The photoresist 101 here can be a positive resist or a negative resist, and the coating of the photoresist 101 can be a dry film pasted on the wafer or a liquid photoresist 101 spin-coated on the wafer. Etching can be wet etching or dry etching.

[0048...

Embodiment 2

[0053] Such as Figure 8 to Figure 16 As shown, a method for etching a deep silicon cavity of a microsystem module specifically includes the following steps:

[0054] 101) Preliminary etching step: deposit a layer of hard mask layer 105 with a thickness ranging from 2 to 10 microns on the upper surface of the wafer, form a preliminary large cavity 104 on the hard mask layer 105 by exposure and development technology, and The etching depth is increased to form a corresponding large cavity 107 .

[0055] The hard mask layer 105 here can adopt various suitable deposition methods such as chemical vapor deposition, physical vapor deposition, and evaporation. The thickness of the deposited hard mask layer 105 can be adjusted arbitrarily to meet good performance requirements. The hard mask layer 105 can be made of various materials with hard mask properties such as silicon dioxide and silicon nitride. The pattern etched out of the hard mask layer 105 can be etched by dry etching o...

Embodiment 3

[0061] Such as Figure 8 , Figure 9 , Figure 17 to Figure 20 As shown, a deep silicon cavity etching method for a microsystem module, the specific test process is as follows:

[0062] 101) Preliminary etching step: coating photoresist 101 on the upper surface of the wafer, the coating thickness ranges from 8 microns to 15 microns, and distributes at least two or more preliminary cavities on the photoresist 101 through exposure and development technology, And the etching depth is increased to form a small cavity 102, and the depth of the small cavity 102 is between 8 microns and 15 microns. The gluing method can be spin coating method or dry film pasting method; the width of the small cavity 102 and the side wall thickness of the small cavity 102 can be adjusted arbitrarily to meet good performance requirements.

[0063] 102) Preliminary shaping step: further increase the etching depth on the processed wafer in step 101), remove the photoresist 101 after the etching is com...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
sizeaaaaaaaaaa
Login to View More

Abstract

The invention discloses a deep silicon cavity etching method of a micro-system module. The deep silicon cavity etching method specifically comprises the following steps: 101) a preliminary etching step, 102) a preliminary shaping step, and 103) a termination layer etching step; the invention provides the deep silicon cavity etching method for efficiently manufacturing the micro-system module, which can solve the problems of structural precision and structural defects.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to an etching method for a deep silicon cavity in a radio frequency microsystem module through which chips are embedded in a silicon adapter board. Background technique [0002] With the development of silicon-based micro-electromechanical (MEMS) and radio-frequency through-silicon via (RF TSV) process technology, three-dimensional heterogeneous integrated microsystem technology has become an important direction for the development of next-generation military highly integrated electronic system technology. Three-dimensional heterogeneous integration is an integration method that embeds chips of different sizes and textures into the silicon cavities on the silicon-based substrate through post-wiring technology to fan out, and then through silicon vias to achieve high-density integration. [0003] However, when a chip with a large width and a large depth is buried on a silicon i...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): B81C1/00H01L21/768
CPCB81C1/00301H01L21/76898
Inventor 郭西
Owner 浙江集迈科微电子有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com