Hardware debugging method, device and system and readable storage medium

Abstract

The invention discloses a hardware debugging method, device and system and a readable storage medium. The method comprises the steps of enabling target equipment to monitor read-write configuration operation of an off-chip PCIe controller, wherein the off-chip PCIe controller is controlled by the debugging upper computer, and the target equipment is equipment based on a JTAG standard; analyzing the read-write configuration operation to obtain a PCIe debugging signal; converting the PCIe debugging signal into a JTAG debugging signal; and performing JTAG debugging by using the JTAG debugging signal. In the method, the method is not limited by a computer host and a JTAG test tool any more, and the equipment debugging requirement can be met directly by multiplexing PCIe. Furthermore, due to the fact that debugging testing can be achieved through the PCIe bus, the number of pins needed by traditional JTAG debugging can be reduced, and occupied equipment space is reduced.

Description

technical field [0001] The present invention relates to the technical field of computer applications, and in particular, to a hardware debugging method, device, system and readable storage medium. Background technique [0002] The JTAG interface of the IEEE1149.1 standard is 4 lines - TMS, TCK, TDI, TDO, which are mode selection, clock, data input and data output lines respectively. The working principle of JTAG can be summed up as follows: define a TAP controller inside the device (specifically, a device chip), and test and debug the internal nodes through a dedicated JTAG test tool. Among them, TAP is a general port, the computer host can access all the data registers and instruction registers provided by the chip through the TAP, and the control of the entire TAP is done through the TAP controller. [0003] It can be seen that the device based on the JTAG debugging principle can be debugged through a computer host or a JTAG test tool. However, in practical applications,...

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Problems solved by technology

[0005] The purpose of the present invention is to provide a hardware debugging method, device, system and readable storage medium. By multiplexing the PCIe interface, the device based on JTAG can be debugged through PCIe, which can solve the problem that the host computer cannot participate and lacks JTAG testing. Difficulties in debugging devices without tools

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