The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.
 See figure 1 , A transmitting terminal of a high-definition digital image transmission system of a traversing machine, including a digital camera 1, a transmitting terminal motherboard 2, a wireless module 3, a data interface 4, a power interface 5 and a USB interface 6. The transmitting terminal motherboard 2 contains data encoding 21, data Group package 22 and total power input 23, wireless module 3 contains radio frequency modulation 31, reactance matching circuit 32 and power amplifier circuit 33, digital camera 1 is connected to data code 21 through data interface 4, data code 21 is connected to data group package 22, data group The package 22 is connected to the RF modulation 31 through the USB interface 6, the RF modulation 31 is connected to the reactance matching circuit 32, the reactance matching circuit 32 is connected to the power amplifier circuit 33, and the total power input 23 is connected to the digital camera 1 and the wireless module 3 through the power interface 5; 4 The MIPI interface is adopted, so that the transmitter motherboard 2 obtains the original video data through this interface.
 See Figure 2-4 , The total power input 23 also includes the front-level protection circuit 231, the mainboard power supply circuit 232 and the wireless module power supply 233. The front-level protection circuit 231 contains the battery interface J01, the fuse F2, the Zener diode D7 and the parallel capacitors C1, C2, C3, Among them, the pin 1 of the battery interface J01 is connected to the pin 1 of the fuse F2, the pin 2 of the battery interface J01 is grounded to GND, the pin 2 of the fuse F2 is connected to the Zener diode D7, and the parallel capacitors C1, C2 and C3 are connected to the two terminals of the Zener diode D7. Terminal, the circuit interface of parallel capacitors C1, C2, C3 is connected to the power supply V_IN; when the battery enters the device through the battery interface J01, the device first passes the fuse F2 for 1A overcurrent protection, and then the Zener diode D7 for overvoltage protection, and then the power supply The V_IN power supply system is generated by filtering the difference between high frequency and low frequency through parallel capacitors C1, C2, and C3.
 The motherboard power circuit 232 contains a CPU, which is connected to 1V1_CORE input power, 1V5_1V35_DDRIO input power, 3V3 input power, and 3V3_CAM input power through the peripheral interface; 1V5_1V35_DDRIO input power supplies the working voltage for the DDR in the CPU, and the 3V3 input power is The CPU shell provides working power, that is, data interface 4, USB interface 6, and provides working power for digital camera 1 through the 3V3_CAM input power;
 The wireless module power supply 233 contains integrated circuits U2, U3, inductors L1, L2, parallel capacitors C6, C7, C8, and parallel capacitors C11, C12, C13. Among them, the pin 3 of the integrated circuit U2 is connected to the input power V_IN, and pin 2 is connected to the inductor. L1, after connecting the inductance L1 to the parallel capacitors C6, C7, C8, connect to the 3V3_WL power supply, the pin 3 of the integrated circuit U3 is connected to the input power V_IN, the pin 2 is connected to the inductor L12, and the inductance L2 is connected to the parallel capacitors C6, C7, C8 and then connected to the 5V0_WL power supply ; When the total power supply is connected through V_IN, the closed-loop feedback circuit is formed through the inductor and the adjustable circuit, the CPU controls the internal switch circuit through this configuration to realize the control of the output voltage, in order to reduce the output voltage ripple, through the parallel capacitors C11, C12, C13 performs high-frequency and low-frequency filtering on the output voltage to make its ripple meet the needs of the module, thereby generating corresponding 3V3_WL and 5V0_WL to supply power to the module.
 See Figure 5 The reactance matching circuit 32 contains resistors R1, R2 and capacitors C1, C2, C3, C4. Among them, pin 2 of resistor R1 is connected to the RF0 interface, pin 1 is connected to pin 4 of the power amplifier circuit 33, and capacitor C1 is connected to the pin of resistor R1. 2 On the circuit interface, the capacitor C2 is connected to the pin 1 circuit interface of the resistor R1, the pin 2 of the resistor R2 is connected to the RF1 interface, the pin 1 is connected to the pin 7 of the power amplifier circuit 33, and the capacitor C3 is connected to the pin 2 of the resistor R2. The capacitor C4 is connected to the circuit interface of pin 1 of the resistor R1, and the pins 18 and 23 of the power amplifier circuit 33 are respectively connected to the antenna ANTENNA1; the π-type resistor-capacitor circuit formed by the resistor R1 and the capacitors C1 and C2 performs signal attenuation for the radio frequency model, which is Achieve good signal amplification. Impedance matching of the radio frequency signal during the attenuation process is performed through the double-transmitting and double-receiving circuit composed of resistors R1, R2 and capacitors C1, C2, C3, and C4 for impedance consistency matching and filtering; and the power amplifier circuit 33 The digital radio frequency signal processed by the reactance matching circuit 32 is amplified, so that the power of the original radio frequency unit is increased from 25 mw to 200 mw, thereby enhancing the transmission distance.
 See Image 6 , The transmitter motherboard 2 also contains a CPU clock circuit 24, a FLASH circuit 25, a DDR memory circuit 26, a MIPI interface circuit 27, a camera socket interface circuit 28, and a USB interface circuit 29. The CPU clock circuit 24 consists of the main control chip CPU, The crystal oscillator body X1, X2, series capacitors C1, C2, series capacitors C130, C131 and resistors R104, R9, R169 are composed, the pin U1 of the main control chip CPU is connected to the pin 1 of the crystal oscillator body X1, and the pin U2 is connected to the resistor R104 in series. The pin 3 of the crystal oscillator body X1, the two ends of the series capacitors C130 and C131 are connected to the pin 1 and pin 3 circuit interface of the crystal oscillator body X1, the pin W2 of the main control chip CPU is connected to the pin 1 of the crystal oscillator body X2, and the pin W1 is connected to the crystal oscillator body Pin 2 of X2, the two ends of the series capacitors C1 and C2 are connected to the pin 1 and pin 2 of the crystal oscillator body X2. One end of the resistor R169 is connected to the 3V3 power supply, the other end is connected to the circuit interface of the resistor R9, and the resistor R9 is connected to the main control The pin P1 of the chip CPU; the crystal oscillator body X1 provides the working clock for the system and peripherals, the crystal oscillator body X2 provides an accurate clock reference for the peripherals that require high clock accuracy, and the 3V3 power supply provides power for the chip and each interface .
 See Figure 7 , FLASH circuit 25 is composed of processing chip U3. Pin 1 of the processing chip U3 is connected to pin R3 of the main control chip CPU, pin 2 is connected to pin P3 of the main control chip CPU, and pin 3 is connected to pin P2 and pin 5 of the main control chip CPU. Connect to pin R2 of the main control chip CPU, pin 6 to resistor R9, and pin 7 to pin P4 of the main control chip CPU; connect to the main control chip CPU via processing chip U3 to obtain the system firmware stored in the external FLASH, and start Then load the firmware into the memory to run.
 See Picture 8 , DDR memory circuit 26 is composed of DDR chips U7, U8 and DDR interface chip U4A. The address bus of DDR chip U7 and U8 is DDR3_A0~DDR3_A14, and the data bus is DDR3_DQ0~DDR3_DQ15. The chip select pin DDR3_CS of DDR interface chip U4A is composed of The main control chip CPU controls; because the DDR memory circuit 26 also contains filter capacitors corresponding to the DDR chips U7, U8 and the DDR interface chip U4A one-to-one, the above-mentioned chip is filtered by the filter capacitor.
 See Picture 9 , MIPI interface circuit 27 is powered by a 3V3 power supply, and pins AB2 and Y2 of the circuit are connected to the camera configuration interface I2C0; through the I2C0 interface, the CPU sends configuration commands to the camera to configure the camera parameters, and the MIPI0 interface is used to obtain the camera transmission Video data;
 See Picture 10 The camera socket interface circuit 28 is composed of socket interface JP2 and Zener diodes D18 and D19. Among them, pin 20 of the socket interface JP2 is connected to the 3V3_CAM power supply, one end of the Zener diode D18 is connected to the pin 18 of the socket interface JP2, and the Zener diode D19 One end is connected to the pin 19 circuit interface of the socket interface JP2, the Zener diode D18 and the other end of the Zener diode D19 are grounded together; the connection between the digital camera 1 and the transmitter motherboard 2 is realized through this interface, and the power supply is provided by the power module 3V3_CAM is powered. In order to avoid electrostatic damage, add ESD devices in this interface, namely, Zener diodes D18 and D19 for electrostatic protection.
 See Picture 11 , USB interface circuit 29 is composed of USB interface J25, capacitor C434, and magnetic bead LB18. After pin 1 of USB interface J25 is serially connected to magnetic bead LB18, connect to 5V0_WL, and one end of capacitor C434 is connected to the circuit interface of pin 1 of USB interface J25. The other end is grounded, and the pins 2 and 3 of the USB interface J25 are connected to the data communication lines USB_DM and USB_DP respectively as USB; through this circuit, the power supply is filtered with high frequency to eliminate high frequency interference, and the wireless connection between USB_DM and USB_DP and USB interface Module 3 communicates.
 The launch method includes the following steps:
 Step 1: Record video and images through the digital camera 1;
 Step 2: Upload the video and images recorded by the digital camera 1 to the main board 2 of the transmitter via the MIPI interface, and generate the original data;
 The third step: compress the original video and image data through the data encoding 21, and after the compressed data is packaged 22 according to the communication protocol, the data required for transmission is generated;
 The fourth step: upload the data to the wireless module 3 via the USB interface 6, and modulate the digital model through the radio frequency modulation 31 to generate a radio frequency signal;
 Step 5: The radio frequency signal passes through the reactance matching circuit 32 to the power amplifier circuit 33, and the radio frequency signal is amplified by the power amplifier circuit 33 and then transmitted through the antenna ANTENNA1.
 To sum up: the transmitting end of the high-definition digital image transmission system of the traversing machine, through the image transmission system composed of the digital camera 1, the transmitting end main board 2 and the wireless module 3, realizes the transmission of 720P high-definition video, avoiding the multiple devices on the same site The occurrence of image cross-connections facilitates the holding of more complex and huge competition content; as the weight of additional sports cameras is eliminated, the weight of the aircraft is reduced, the control of the players is improved, and the delay for high-definition image transmission is reduced, making the aircraft realistic The screen can be transmitted to the players more quickly, providing them with valuable decision-making time.
 The above are only preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited to this. Anyone familiar with the technical field within the technical scope disclosed by the present invention, according to the technical solution of the present invention Equivalent replacements or changes to its inventive concept should all fall within the protection scope of the present invention.