A method, system and storage medium for hierarchical design chip timing convergence

Abstract

The present application provides a method and system for hierarchical design chip timing convergence, wherein the method includes: completing the first standard cell placement according to the design data of the whole chip; completing the second standard cell placement according to the sub-module design data; wherein , the submodule design data includes a submodule timing model; compare the submodule timing model and the physical delay information at the submodule port to obtain missing timing arc data; perform scripting according to the timing arc data and time information Transformation to complete the timing closure of sub-module interface design. This technical solution can avoid the problem of prolonging the chip design cycle due to missing ETM model timing arcs or inaccurate delay information in the early stage of design, effectively shortening the design cycle, speeding up the process of chip listing, and promoting the time to market of products.

Description

technical field [0001] The invention relates to the technical field of chip design, in particular to a method, system and storage medium for hierarchically designing chip timing convergence. Background technique [0002] As the difficulty of chip design increases, the scale expands, and the process size shrinks, the convergence speed of chip physical implementation directly affects the time to market of mass production of chips, so it is very important to improve the convergence speed of chip physics. At present, the physical design of medium and large-scale chips will adopt a parallel hierarchical design strategy. The first level needs to use the physical model and timing model provided by the second level in the design process, and the second level needs to use the third level in the design process. physical and timing models. The timing model uses the extracted timing model, referred to as ETM. ETM is extracted by second-level or third-level designers through EDA tools....

AI Technical Summary

Problems solved by technology

[0003] The existing method of generating ETM will have the problems of loss of timing arc, loss of physical delay of data link, inability to reflect physical delay of constant path, inconsistency between extracted physical link delay and first level; loss of timing arc or physical delay of data link will cause As a result, the timing closure efficiency between the first level and the second level is greatly reduced. The inconsistency between the extracted physical link delay and the first level will cause timing violations not to be seen during the first level optimization process, but in the later stage of design completion Take the very serious timing as an example in the splicing stage of the first level and the second level, which will cause the timing convergence of the chip and need to re-iterate to converge.

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