Hierarchical design chip timing convergence method and system and storage medium

Abstract

The invention provides a hierarchical design chip time sequence convergence method and system. The method comprises the steps of completing first standard unit placement according to design data of awhole chip; completing the second standard unit placement according to the design data of the sub-modules, wherein the sub-module design data comprises a sub-module time sequence model; comparing thesub-module time sequence model with the physical delay information at the sub-module port to obtain missing time sequence arc data; According to the time sequence arc data and the time information, script language conversion is carried out, and sub-module interface design time sequence convergence is completed. According to the technical scheme, the problem that the design period of the chip is prolonged due to time sequence arc loss or inaccurate delay information of the ETM model can be avoided at the early stage of design, the design period is effectively shortened, the marketing process ofthe chip is accelerated, and the product appearance time is promoted.

Description

technical field [0001] The invention relates to the technical field of chip design, in particular to a method, system and storage medium for hierarchically designing chip timing convergence. Background technique [0002] As the difficulty of chip design increases, the scale expands, and the process size shrinks, the convergence speed of chip physical implementation directly affects the time to market of mass production of chips, so it is very important to improve the convergence speed of chip physics. At present, the physical design of medium and large-scale chips will adopt a parallel hierarchical design strategy. The first level needs to use the physical model and timing model provided by the second level in the design process, and the second level needs to use the third level in the design process. physical and timing models. The timing model uses the extracted timing model, referred to as ETM. ETM is extracted by second-level or third-level designers through EDA tools....

AI Technical Summary

Problems solved by technology

[0003] The existing method of generating ETM will have the problems of loss of timing arc, loss of physical delay of data link, inability to reflect physical delay of constant path, inconsistency between extracted physical link delay and first level; loss of timing arc or physical delay of data link will cause As a result, the timing closure efficiency between the first level and the second level is greatly reduced. The inconsistency between the extracted physical link delay and the first level will cause timing violations not to be seen during the first level optimization process, but in the later stage of design completion Take the very serious timing as an example in the splicing stage of the first level and the second level, which will cause the timing convergence of the chip and need to re-iterate to converge.

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