System-in-package structure and method of making the same

Abstract

The invention provides a system-level packaging structure and a manufacturing method thereof. The system-level packaging structure includes: at least one bare chip, at least one passive device pre-connector, a second conductive block of a conductive frame, a first plastic packaging layer, and rewiring layer and the second plastic packaging layer, the bare chip includes a plurality of pads, and the pads are located on the front side of the bare chip; the passive device pre-connector includes the passive device and the first conductive block of the conductive frame, the passive device includes electrical connection points, and the electrical The connection point is directly connected to at least part of the first conductive block; the first plastic encapsulation layer covers the bare chip, the passive device pre-connector and the second conductive block; The electrical connection point of the device and the second conductive block are electrically connected; the second plastic encapsulation layer covers the redistribution layer. According to the embodiment of the present invention, the plastic packaging and electrical interconnection of the bare chip and the passive device can be completed in the same process. On the one hand, the production efficiency can be improved, and on the other hand, the miniaturization of the system level packaging structure can be realized.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a system-level packaging structure and a manufacturing method thereof. Background technique [0002] System-in-package technology (SIP) refers to the integration of multiple chips and passive components in a package structure to achieve a basically complete function. Compared with the traditional separate packaging structure of a single chip and passive components, the system-in-package structure can achieve a smaller package volume and lower packaging cost. [0003] The existing system-level packaging structure adopts a side-by-side or superimposed method for different chips and passive devices in the same lead frame. The interconnection between the chip and passive devices is realized by wires or copper sheets. [0004] However, on the one hand, the wire bonding process is complicated and the production efficiency is low. On the other hand, the metal leads are...

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Problems solved by technology

[0004] However, on the one hand, the wire bonding process is complicated and the production efficiency is low. On the other hand, the metal leads are roughly parabolic, and the highest point is higher than the upper surface of the chip, which results in a high package height, which is not conducive to reducing the thickness of the package structure.

In addition, the layout and connection methods between chips and between chips and passive devices are not conducive to reducing the planar size of the package structure

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