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Substrate carrier and substrate carrier stack

A substrate and carrier technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as cost and impact on wafers

Pending Publication Date: 2021-01-01
MURATA MASCH LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The process can affect a significant portion of processed wafers, resulting in significant cost

Method used

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  • Substrate carrier and substrate carrier stack
  • Substrate carrier and substrate carrier stack
  • Substrate carrier and substrate carrier stack

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0168] figure 1 is a perspective view of a first preferred embodiment of a substrate carrier stack 10 comprising a plurality of substrate carriers 12 stacked on top of each other, wherein the substrate carriers are stacked on a substrate carrier stack base 14 and a cover 16 of the substrate carrier stack are stacked on a substrate carrier. According to terminology such as US 2017 / 0372930 A1, a substrate carrier stack 10 may be denoted as a "substrate holder" comprising a plurality of separate "modules" (i.e. substrate carriers 12), which may be denoted as a "top module". " or "cap" or "upper cap" or similar base 14 and may be denoted as "bottom module" or "bottom piece" or "bottom cap" or similar cover 16. In the absence of base 14 and cover 16, a stacked substrate carrier 18, ie a plurality of individual substrate carriers 12 stacked on top of each other, may be denoted as a "stacked module".

[0169] According to a preferred embodiment of the present invention, the base 14...

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PUM

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Abstract

A substrate carrier stack includes substrate carriers which are stacked or stackable on each other and carry substrates within an inner accommodation space of the substrate carrier stack. The substrate carrier stack includes at least one first purging channel and at least one second purging channel, which extend vertically parallel to the inner accommodation space at opposing sides thereof, and purging structures which enable horizontal purging flows within the substrate carrier stack through spaces between substrates held by the substrate carriers. The substrate carriers each include an outercarrier frame provided with a seat to carry a substrate, wherein the outer carrier frame extends around the first and second purging channels and the inner accommodation space.

Description

[0001] Cross References to Related Applications [0002] This application claims German Patent Application No. 20 2018 103 662.9 filed June 27, 2018, U.S. Patent Application No. 16 / 185,541 filed November 9, 2018, and German Patent Application No. Priority of .20 2019 101 794.5. The entire content of each of these applications is hereby incorporated by reference. technical field [0003] The present disclosure generally relates to the handling, storage, handling and processing of substrates in semiconductor production. In particular, the present disclosure relates to the handling, storage, handling and processing of substrates in the form of raw or pre-processed or processed semiconductor wafers. However, the substrate to be handled or stored may also be a mask or reticle or the like containing, for example, a pattern required for patterning a semiconductor wafer in the manufacture of semiconductors or semiconductor circuits information. [0004] Due to the introduction of ...

Claims

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Application Information

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IPC IPC(8): H01L21/673
CPCH01L21/67346H01L21/67383H01L21/67389H01L21/67376
Inventor T·朔贝尔B·拉赫巴赫C·沃汉卡Y·芬纳G·多维德J·菲德斯
Owner MURATA MASCH LTD