Multi-lane serializer device

Abstract

A multi-lane serializer device 1 is provided with a plurality of serializer circuits 101 to 10N, and a control unit 20. A phase difference detection unit of each of the serializer circuits detects a phase difference between a load signal and a first clock, and outputs an abnormality sensing signal to the control unit 20 if the detected phase difference is abnormal. The control unit 20, when the abnormality sensing signal is received from any of the serializer circuits, sends a mass reset instruction signal to all of the serializer circuits. In all of the serializer circuits, a reset signal generation unit, when the mass reset instruction signal outputted from the control unit 20 is received, passes a reset instruction signal to a load signal generation unit and causes a load signal generation operation in the load signal generation unit to be reset.

Description

technical field [0001] The present invention relates to a multi-lane serializer device including a multi-lane serializer circuit. Background technique [0002] The serializer circuit serializes parallel data input in synchronization with the first clock, and outputs the serial data in synchronization with the second clock. The serializer circuit latches the parallel data at the timing indicated by the load signal having the same cycle as the first clock, and outputs the latched data as serial data in synchronization with the second clock. The cycle of the second clock is shorter than the cycle of the first clock. The load signal has the same period as the first clock and is generated based on the second clock (see Patent Document 1). [0003] In the serializer circuit, in order to securely latch the parallel data, it is important to combine the first clock and the load signal according to the respective margins of the setup time and the hold time during the latch operation...

AI Technical Summary

Problems solved by technology

[0006] When there is no communication line from the receiving side to the sending side, the fact that the bit error rate is high cannot be notified from the receiving device to the serializer circuit on the sending side, and the serializer circuit cannot use the first clock and load signal The phase difference between restores to within a reasonable range

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