Chip subsystem verification method and device

A verification method and sub-system technology, which are applied in the field of chip sub-system verification methods and devices, and can solve problems such as the influence of sub-system functions and the inability to construct performance scenarios.

Pending Publication Date: 2021-04-20
JLQ TECH CO LTD
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  • Abstract
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  • Claims
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Problems solved by technology

However, if the C test performance verification is performed on the subsystem alone, a specific performance scenario cannot be constructed
If the subsystem requires high memory bandwidth, the delay of other systems coupled to the subsystem will have a significant impact on the subsystem function.

Method used

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  • Chip subsystem verification method and device
  • Chip subsystem verification method and device

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Embodiment Construction

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings that need to be used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present application, and those skilled in the art can also apply the present application to other similar scenarios. Unless otherwise apparent from context or otherwise indicated, like reference numerals in the figures represent like structures or operations.

[0027] As indicated in this application and claims, the terms "a", "an", "an" and / or "the" do not refer to the singular and may include the plural unless the context clearly indicates an exception. Generally speaking, the terms "comprising" and "comprising" only suggest the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list, and ...

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Abstract

The invention provides a chip subsystem verification method and device. The method comprises the following steps: constructing a test sequence based on VIP testing, a virtual sequencer and an excitation host, wherein the virtual sequencer is used for receiving the test sequence and is coupled with the excitation host, and the excitation host is suitable for inputting excitation to a to-be-verified subsystem of a chip; constructing a simulation platform based on a C test, wherein the simulation platform is suitable for providing configuration information for the subsystems; constructing a VIP test-based response slave for replacing a memory and a storage controller; and forming a verification environment by using the virtual sequencer, the excitation host and the response slave, and forming a verification platform together with the test sequence and the simulation platform to verify the subsystem.

Description

technical field [0001] The present invention mainly relates to the field of chip verification, in particular to a chip subsystem verification method and device. Background technique [0002] With the development of chip integration trend, more and more IP (Intellectual Property) modules and subsystems (Subsys) need to exchange data with DDR through internal high-speed bus. Due to the development of IP Vendor technology and the independence of services, differentiated subsystems have also become the key to reflecting the core competitiveness of System on Chip (SoC). However, the bottleneck that restricts the performance of subsystems in actual engineering is often concentrated during the frequent access of DDR. How to verify the bugs of subsystems in DDR performance scenarios has become a challenging problem in SoC system integration. [0003] The system verification platform of SoC chips usually has two verification strategies: C test (C test) and UVM (Universal Verificatio...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22G06F30/398G06F111/04G06F111/08G06F115/10
Inventor 赖龙麟何世超黄耀华
Owner JLQ TECH CO LTD
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