Chip subsystem verification method and device

Abstract

The invention provides a chip subsystem verification method and device. The method comprises the following steps: constructing a test sequence based on VIP testing, a virtual sequencer and an excitation host, wherein the virtual sequencer is used for receiving the test sequence and is coupled with the excitation host, and the excitation host is suitable for inputting excitation to a to-be-verified subsystem of a chip; constructing a simulation platform based on a C test, wherein the simulation platform is suitable for providing configuration information for the subsystems; constructing a VIP test-based response slave for replacing a memory and a storage controller; and forming a verification environment by using the virtual sequencer, the excitation host and the response slave, and forming a verification platform together with the test sequence and the simulation platform to verify the subsystem.

Description

technical field [0001] The present invention mainly relates to the field of chip verification, in particular to a chip subsystem verification method and device. Background technique [0002] With the development of chip integration trend, more and more IP (Intellectual Property) modules and subsystems (Subsys) need to exchange data with DDR through internal high-speed bus. Due to the development of IP Vendor technology and the independence of services, differentiated subsystems have also become the key to reflecting the core competitiveness of System on Chip (SoC). However, the bottleneck that restricts the performance of subsystems in actual engineering is often concentrated during the frequent access of DDR. How to verify the bugs of subsystems in DDR performance scenarios has become a challenging problem in SoC system integration. [0003] The system verification platform of SoC chips usually has two verification strategies: C test (C test) and UVM (Universal Verificatio...

AI Technical Summary

Problems solved by technology

However, if the C test performance verification is performed on the subsystem alone, a specific performance scenario cannot be constructed

If the subsystem requires high memory bandwidth, the delay of other systems coupled to the subsystem will have a significant impact on the subsystem function.

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