A Physical Realization Structure of High Precision Data Delay Line

Abstract

The invention discloses a physical realization structure of a high-precision data delay line, including a substrate and several levels of elements installed on the substrate; elements in each level of elements include a buffer, an inverter, and a first NAND gate , the second NAND gate and the third NAND gate; the elements in the nth level element are symmetrical to the elements in the (n-1)th level element along the X axis; the third NAND gate of each level element is adjacent to it The connection lines between the third NAND gates of the element are of the same length; the connection lines between the first NAND gate of each level of element and the buffers of its adjacent elements are of the same length. The present invention arranges each element according to the connection relationship between elements of different levels and elements in each level, so that the physical connection between elements of adjacent levels is not affected by crosstalk of other signals, and each element of the data delay line is satisfied. The same requirement for stage shifting improves the implementation efficiency of the data delay line.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a physical realization structure of a high-precision data delay line. Background technique [0002] The main function of the digital delay line (Digital Delay Line, DDL) is to perform a specific delay on the digital signal to achieve a certain phase shift characteristic at the output. The advantage of the digital delay line is that it is process compatible. Digital delay lines are widely used in communication systems, measuring instruments, color TV systems, etc. With the improvement of communication bandwidth speed and further improvement of measurement accuracy, the accuracy requirements of digital delay lines also increase. [0003] For the physical implementation of digital delay lines, digital physical designers generally use EDA tools to complete automatic placement, capture and compare the physical delay lengths of each level of input through timing reports, ...

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Problems solved by technology

[0003] For the physical implementation of digital delay lines, digital physical designers generally use EDA tools to complete automatic placement, capture and compare the physical delay lengths of each level of input through timing reports, and adjust the size of standard unit drivers and final winding through ECO. Meet the requirement that the physical delay lengths are equal, but the absolute physical delay lengths between different components are often uncontrollable, which will cause a certain deviation in the phase shift of each stage

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