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Data decoding device, accelerator, and system on chip

A decoding device and accelerator technology, applied in the field of data processing, can solve the problems affecting the processing efficiency of accelerator computing tasks, low decoding efficiency, limited transmission bandwidth, etc.

Active Publication Date: 2021-05-28
SHANGHAI SENSETIME INTELLIGENT TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

With the increase of shared computing tasks, the accelerator needs to frequently access the data in the memory, and the transmission bandwidth between the accelerator and the memory is limited, resulting in the data transmission between the accelerator and the memory gradually becoming a constraint to improve the calculation speed and energy efficiency of the neural network. important question
[0003] In order to save the transmission bandwidth between the accelerator and the memory, it is usually necessary to compress the data, generate coded data and then transmit it; when decoding the coded data, the decoding efficiency is low, which affects the computing task processing efficiency of the accelerator

Method used

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  • Data decoding device, accelerator, and system on chip
  • Data decoding device, accelerator, and system on chip
  • Data decoding device, accelerator, and system on chip

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Embodiment approach

[0226]In another embodiment, another implementation manner for the data filler 30 to determine the filling position of the filled index data relative to the plurality of original index data is provided, including:

[0227] Based on the image size information and filling width information, determine a filling data pattern corresponding to each filling position in the plurality of filling positions;

[0228] Based on the filling data pattern of each filling position in the plurality of filling positions and the position of the plurality of original index data in the index sequence, the filling position of the filling index data relative to the plurality of original index data is determined.

[0229] Here, the padding data pattern is a predetermined template based on the image size information and padding width information, and then based on the template and multiple original index data obtained in each cycle, the position in the index sequence is determined to determine the paddi...

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Abstract

The invention provides a data decoding device, an accelerator and a system on a chip. The data decoding device is used for decoding coded data, and the data decoding device comprises a decoder and a plurality of selectors connected with the decoder, wherein the decoder is used for obtaining a plurality of target index data, generating data selection control information corresponding to each piece of target index data in the multiple pieces of target index data, and transmitting the data selection control information corresponding to each piece of target index data to a selector corresponding to each piece of target index data; and the selectors are each used for obtaining a decoding result corresponding to each piece of target index data based on the data selection control information corresponding to each piece of target index data transmitted by the decoder. The device can improve the decoding efficiency of the coded data.

Description

technical field [0001] The present disclosure relates to the technical field of data processing, and in particular, to a data decoding device, an accelerator, and a system on chip. Background technique [0002] In the field of deep learning, accelerators are usually used to implement training tasks of neural network models or accelerated execution of data processing tasks. For example, multiple accelerators are respectively connected to the central processing unit (CPU), and the central processing unit can assign different computing tasks to different accelerators; after any accelerator receives the computing tasks assigned by the central processing unit, , read the data stored in the memory based on the computing task, execute the corresponding computing task based on the read data, and write the result generated by executing the computing task into the memory after executing the corresponding computing task. With the increase of shared computing tasks, the accelerator nee...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L29/06
CPCH04L69/04
Inventor 谭旭高洋
Owner SHANGHAI SENSETIME INTELLIGENT TECH CO LTD