Digital currency processor chip measuring method based on programmable power supply

A technology of digital currency and measurement method, applied in the direction of digital circuit testing, measuring electricity, measuring devices, etc., can solve the problems of increasing the risk of idle equipment in test plants, sacrificing accuracy, and poor measurement accuracy of super-current programmable power supply instruments.

Pending Publication Date: 2021-06-01
SANDTEK SEMICON TECH (SHANGHAI) LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This will increase the risk of idle equipment in the test factory and indirectly increase the cost
The shortcomings of the ultra-high current programmable power supply instrument's poor measurement accuracy at low current levels also sacrifice the accuracy of this type of chip for static power consumption testing

Method used

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  • Digital currency processor chip measuring method based on programmable power supply
  • Digital currency processor chip measuring method based on programmable power supply
  • Digital currency processor chip measuring method based on programmable power supply

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Embodiment

[0041] Such as image 3 , Figure 4 As shown, the working voltage of the DUT under test is 0.9V, and the expected maximum current is 9.5A. In this way, when the working mode test is performed, the main control power channel and 9 slave power channels are configured as a cluster mode. V force =0.9V, the voltage is dominated by the main control unit; I DUT =9.5A, N=9; then I measure工作 =9.5 / (9+1)=0.95A=I copy ; Calculate I in this way slave-1 = I slave-2 = I slave-3。。。 = I slave-N = I copy =0.95A, then I DUT = I master + =(N+1)*I master ; When performing a low power consumption mode test, to measure the real consumption current, you only need to read the operating current on the main control power supply channel, that is, I measure = I copy .

[0042] The present invention can flexibly configure the number of channels in the cluster mode according to the requirements of the digital currency processor chip to be tested, and optimize the test resources; the master ...

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Abstract

The invention relates to the technical field of semiconductor testing, in particular to a digital currency processor chip measuring method based on a programmable power supply. The specific test method comprises the following steps: S1, a test carrier plate is connected with a programmable power supply; S2, a master power supply channel and slave power supply channels are set in the programmable power supply; S3, when the working mode of a digital currency processor chip is tested, the master power supply channel and the slave power supply channels are automatically opened; S4, I(master<work>) is read, and the total consumed current I(measure<work>) is equal to I(master<work>) * N; and S5, when the low-power-consumption mode test of the digital currency processor chip is carried out, the static current I(measure) is equal to I(master). Compared with the prior art, the programmable power supply is connected to the test carrier plate of the existing logic type automatic test machine, and the programmable power supply is configured into a parallel connection form of one master power supply channel and a plurality of slave power supply channels, so that the number of the channels can be flexibly configured according to the requirements of a tested chip.

Description

technical field [0001] The invention relates to the technical field of semiconductor testing, in particular to a measuring method for a digital currency processor chip based on a programmable power supply. Background technique [0002] In recent years, digital currency and blockchain technology and their applications have driven a new field in the semiconductor market. This field has optimized a brand-new chip design and manufacturing idea for its special application, and it also poses different challenges to the traditional chip packaging and testing industry. [0003] The digital currency processor chip is different from the traditional system-on-chip (SOC). It does not require a large number of high-speed interfaces. Most of the functional tests are built-in tests (BIST). Therefore, for automatic test machines, there is no need to provide A large number of high-speed digital test channels. Only a small number of digital channels are needed to configure the internal regi...

Claims

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Application Information

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IPC IPC(8): G01R31/3177G01R31/317
CPCG01R31/3177G01R31/31721Y02D10/00
Inventor 魏津张经祥徐润生
Owner SANDTEK SEMICON TECH (SHANGHAI) LTD
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